K65 Allowing for Cache and DMA coherence

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K65 Allowing for Cache and DMA coherence

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unknowncoder
Contributor III

Background

  • I am looking at enabling the code cache controller on the K65 to improve performance.
  • I utilize DMA for peripheral to memory and memory to peripheral transfer.
  • I know cache and DMA don't normally work good together and the normal operation is to invalidate the cache before/after, read/write respectively.

Question

  • From the Table 30-1 it shows that SRAM is non-cacheable. Given this if I make sure that all access with DMA occurs within SRAM would I need to invalidate the cache still?

Thanks

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

Yes, you are right. SRAM in K65 is a kind of TCM. Its speed is same as M4 kernel. It needn't cache.

Regards,

Jing

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unknowncoder
Contributor III

Are both upper and lower memory tightly coupled memory to the core? 

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

Yes.

Regards,

Jing

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