K64F I2S Transmit avoiding underun

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K64F I2S Transmit avoiding underun

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m_lee23
Contributor I

I am trying to transmit via I2S from my K64F. I do not full understand this section of the reference material:

If the Transmit FIFO is empty, the TDR [Transmit Data Register] must be written at least three bit clocks before the start of the next unmasked word to avoid a FIFO underrun.

Whenever I try to send data I notice the FIFO Error Flag (which indicates if underrun has occurred) is set, however I am not sure how to accomplish what it is described above. 

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi m.lee23

This error occurred because in your project you are trying to send data faster than it could write in FIFO, Are you using SDK drivers?. let me explain a little more;

This note that you mention is a reference that your FIFO needs time (3 bit clocks) before you attend to transmit something, because you could attend to transmit a empty FIFO. Transmit channel included a FIFO of size 8, In order to avoid underrun you normally fill your FIFO writing your first 8 values and then start transition, and you set a watermark that tell your MCU that it need fill up TDR FIFO register before it goes empty, for example, in a watermark of 4, you start transmission and when you just have 4 data in your FIFO, with a interrupt detect (FRF request flag) you start to write data to TDR. This method will ensure that you always have data in FIFO, because it will continue writing data while your FIFO number is less or equal to your watermark.

Hope this information helps you, please let me know if you have any question on this. I also recommend you to download and check SDK drivers.

Have a great day,
Jorge Alcala

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m_lee23
Contributor I

I am working with mbed, editing the registers using the mbed structs.

So you are saying I need to fill the fifo before starting to transmit. Then enable transmission, then continue to write as the interrupt occurs. 

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi m.lee23

It is not needed to fill your fifo, but it is to write new values at least three bit clock before the next value is shifted, this is a good practice, you need to be sure that you FIFO has always values, so your FIFO will not be empty when a new transmission request arrive, triggering a FIFO underrun


Have a great day,
Jorge Alcala

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