K64 UART in STOP mode?

[paulderocco]

The K64F Sub-Family Data Sheet (Rev 3) p14 lists an IUART current adder of 66uA when MCGIRCLK is the clock source. The description of this parameter says it is "measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption."

I don't see anywhere in the Reference Manual (Rev 2) a way to allow the UART to continue to function while the CPU is stopped. Section 52.1.2 says the UART runs when the CPU is in Run Mode, that it may run or be halted when the CPU is in Wait Mode depending upon C1[UARTSWAI], and is halted when the CPU is in Stop Mode.

So what does that current adder spec refer to? Is there or isn't there a way to stop the CPU, and have the UART start it up again when a character is received? What I'd really like to do is use the 4MHz IRC for the UART, so that I can stop the crystal OSC module while the CPU is halted.

[mjbcswitzerland]

Hi Paul

The UARTs have an interrupt on an Rx edge, which can be used to wake from various low power modes:

UARTx_BDH |= UART_BDH_RXEDGIE;

// enable wakeup on RxD falling edge

There is a report on using UARTs in various low power statee here: Using Kinetis Low Power Stop Modes with unrestricted UART operation - a report

The uTasker Kinetis project automatically supports low power modes and UART handling so that transitions between power modes are automated without UART loss (as long as the particular low leakage mode can wake up fast enough to not miss Rx bits - STOP mode is no problem as long as the clock source doesn't get stopped).

Regards

Mark

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