K64 SPI Read problem

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K64 SPI Read problem

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alekseystarovoy
Contributor I

Hi.

I am having a problem using K64 device and doing SPI read.
All of the examples that I found on SPI saying to send 0xFF to SOUT line as a dummy write to get a read back.
So, what it does, it keeps SOUT line high and reads all of the toggling in the SIN line.
And this all works great, but the problem is, that my device that I am trying to talk require SOUT line to be LOW for it to
for it to respond correctly.

However, when I send 0x00 as a dummy write, and I can see my logic analyzer shows me correct response from the device, I cannot get correct readback from POPR register. Most of the time it is giving me bunch of zeros. 

I there anybody who experienced same problem, and the way of resolving it?

Thanks. 

-Lex

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2 Replies

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alekseystarovoy
Contributor I

Thanks Jing for the response.

I had to make a BitBang routine to have it work, but I still winder why hardware SPI does not work like that?
Here are my code for initialization and read:

void Spi_init( void )
{
   SIM_SCGC6 |= SIM_SCGC6_SPI0;

   PORTA_PCR6 |= PORT_MUX_GPIO;  //  CS1
   PORTA_PCR8 |= PORT_MUX_GPIO; //  CS2
   PORTA_PCR10 |= PORT_MUX_GPIO; // CS3

   GPIOA_PDDR |= (1 << 6)|(1<<8)|(1<<10); //set to OUT
   GPIOA_PDOR |= (1 << 6)|(1<<8)|(1<<10); // set to HIGH

   PORTD_PCR3 |= PORT_MUX_ALT2; // SPI2_SIN 
   PORTD_PCR2 |= PORT_MUX_ALT2 | PORT_DSE_HIGH | PORT_PE | PORT_PS_UP_ENABLE; // 
   PORTD_PCR1 |= PORT_MUX_ALT2 | PORT_DSE_HIGH | PORT_PE | PORT_PS_UP_ENABLE; // SCLK

   SPI0_MCR |= (SPI_MCR_MSTR);
   SPI0_MCR &= ~(SPI_MCR_DIS_RXF | SPI_MCR_DIS_TXF );// enable FIFOs
   SPI0_CTAR0 = (SPI_CTAR_ASC_4 | SPI_CTAR_PBR_7 | SPI_CTAR_DBR | SPI_CTAR_FMSZ_16 |
   SPI_CTAR_PDT_7 | SPI_CTAR_BR_8 | SPI_CTAR_CPHA | SPI_CTAR_CPOL | SPI_CTAR_PCSSCK_3 ); // 

   SPI0_MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT); //enable SPI and start transfer
}

unsigned short spiread(unsigned char chn, unsigned short addr )
{
   unsigned short rread = 0;
   unsigned int cs;
   if( chn == 1 ){
      cs = 1 << 6;
   }
   else if( chn == 2 ){
      cs = 1 << 8;
   }
   else if( chn == 3 ){
      cs = 1 << 10;
   }
   else
      cs = 0;
   GPIOA_PCOR = cs;

   SPI0_MCR |= SPI_MCR_HALT;
   SPI0_MCR |= SPI_MCR_CLR_RXF | SPI_MCR_CLR_TXF;
   SPI0_SR |= (SPI_SR_EOQF | SPI_SR_TFUF | SPI_SR_TFFF | SPI_SR_RFOF | SPI_SR_RFDF |    SPI_SR_TCF); //clear the status bits (write-1-to-clear)
   SPI0_MCR &= ~SPI_MCR_HALT;

   SPI0_PUSHR = ((addr | SPI_PUSHR_CONT | SPI_PUSHR_PCS0 | SPI_PUSHR_CTAS_CTAR0) | 0x8000);
   while( !(SPI0_SR & SPI_SR_RFDF) ){};
   (void)SPI0_POPR;
   SPI0_SR = SPI_SR_RFDF; // clear the reception flag (not self-clearing)


   SPI0_PUSHR = ( 0x0000 | SPI_PUSHR_PCS0 | SPI_PUSHR_CTAS_CTAR0 | SPI_PUSHR_EOQ );
   while( !(SPI0_SR & SPI_SR_RFDF) ){};
   rread = SPI0_POPR;
   SPI0_SR = SPI_SR_RFDF; // clear the reception flag (not self-clearing)

   Pause(100);

   GPIOA_PSOR = cs;
   return rread ;

}

Can you look at my code and tell if you see something.

Thanks and best Regards.
Aleksey

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86 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi Aleksey,

It sounds strange. As you can see in the reference manual, what it writes to SOUT has no impact on SIN. I think the problem may caused by error setting. You can try the example frdmk64f_dspi_interrupt which you can find in sdk. In this example , one dspi instance used as DSPI master and another dspi instance used as DSPI slave in the same board. You can simulate your device by the slave instance.

Regards,

Jing

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