K64 MDC seems to be inverted

[rogerchaplin]

I'm having trouble bringing up Ethernet in my design. It uses the MK64FN1M0VLQ12 and a Micrel KSZ8081 PHY. I have an interactive shell on a serial port and I added commands to peek, poke, and dump PHY registers. I can't seem to write PHY registers.

I used a scope to look at MDC and MDIO while peeking register 0, picture is attached. It looks like the K64 is changing MDIO on the rising edge of MDC, and not on the falling edge as it ought to be. The cursors on the scope trace show the MDIO is technically meeting the hold time spec: the KSZ8081 needs 4ns and I'm getting 16ns. But this just looks wrong.

There's nothing Ethernet related in the latest errata for this part (1N83J). Can somebody help me figure out what's going on? Thanks.

[Hui_Ma]

Hi Roger,

Freescale FRDM-K64F board is also using the same KSZ8081RNGCA Ethernet PHY chip, you could find FRDM-K64F Ethernet application from KSDK software.

The KSDK software also provides KSZ8081 PHY driver (fsl_phy_driver.c & fsl_phy_driver.h), which located at lwip example demo folder, such as:

C:\Freescale\KSDK_1.2.0\examples\frdmk64f\demo_apps\lwip\lwip_ping_demo\ping_bm

Wish it helps.

Have a great day,
Ma Hui

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