# K60 input leakage current when Vin > Vih

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## K60 input leakage current when Vin > Vih

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Contributor II

Hi all,

Page 15 of the K60 data sheet gives the input leakage current for different input voltages on the digital (and other inputs).  (I am looking at rev 5 of the datasheet, K60 Sub-Family, Rev5, 10/2013, K60P144M120SF3.pdf).

This shows that the input leakage for Vin<Vil is the sort of values expected (sub uA).  It also shows that when Vin=Vdd the input leakage is as expected.  But for Vil < Vin < Vdd the input leakage can rise a lot.

Surely there is a band just below Vin=Vdd where we can do worst case design assuming the input leakage is not so extreme?  Spec suggests that at Vdd=3.3V we could see input leakages of ~23 uA for Vih < Vin < Vdd (scaling between Vdd=3 and Vdd=3.6V).

Is the information in the datasheet correct or is there a problem in the datasheet? An equality condition (Vin=Vdd) in the spec is useless; we are dealing with the real world here not some mathematical situation; under worst case design I can't assume equality!

I fully understand that between Vil and Vih there could be poor specs (such as input leakage currents and an increase in the chips quiescent current).  But the rather poor input leakage spec applying above Vih is surprising.

Ian

Message was edited by: Ian Wilson Changed subject to reflect the real issue

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• ### Kinetis K Series MCUs

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NXP TechSupport

Dear Ian Wilson,

generally, we can use a CMOS model to simulate the input circuit, the top is PMOS, the bottom the NMOS, when the input logic is HIGH(3.3V), the PMOS is off, the NMOS is on, the output is low, when the input is low(GND), the PMOS is on, the NMOS is off, the output is HIGH.

In other words, when the input is low(in the case VSS ≤ VIN ≤ VIL as the data sheet says  )or HIGH(in the case Vin=VDD), the input leakage current in both cases is very low, as the data say is 0.5uA at most.

when the input voltage is neither GND nor VDD, it is complex, for an extreme example, the VDD is 3.3V, the input voltage Vin is 1.65V, in the case, both the NMOS and PMOS will be both on, the leakage current will rise lot as the data sheet says, it may be 20uA. If we draw a curve between the current(Y axis) and input voltage(X axis), the curve will be like a normalized distribution curve, when the input voltage is GND or VDD, the current is low, at the middle voltage, the current will reach at it's peak.

In conclusion, for the digital circuit, we require that the input voltage should be HIGH(VDD) or LOW(GND), the middle voltage should be avoided. If you input a middle voltage, the leakage current will be high.

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Contributor V

I think Ian's point is that we expect good leakage for Vin<Vil (normal low condition) and Vin>Vih (normal high condition). But the datasheet actually specifies for Vin<Vil (normal low condition) and Vin=Vdd (perfect high condition). This is not usual. His question is, what is the leakage when Vin=Vih? We would expect it to be good (just like when Vin=Vil) but reading the datasheet strictly, we have to assume it is very bad. This is not normal.

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Contributor II

Thank you Matthew.  You are correct. The issue is the datasheet assumes a perfect high voltage of Vdd.  I have never seen this in a datasheet before (in 30 years of professional electronics development).

(A collegue said it must have been the intern that wrote this datasheet.)

@

What is the leakage for Vin >= Vih?

You did not answer this question, I am sorry if I wasn't clear.  I did try to be. But if the K60 really does have such poor specified performance when Vin>Vih the part is terrible. I am betting it is a datasheet error but without confirmation I can't do worst case design.

As I wrote, I fully underdstand that specs may be poor when Vil<Vin<Vih, but it is a *big* issue if they are poor when Vin>Vih.

I think it is a datasheet error rather than a device issue but I need to have confirmation of this.  I am surprised this has not come up before and the document fixed.  If it is real then I am surprised the product remains on the market.

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Contributor II

I just realised that I may have caused confusion with the subject I put for the thread.  It should have been:

# K60 input leakage current when Vin > Vih

(so Vih rather than Vil)

Sorry for any confusion.

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NXP TechSupport

The data sheet only lists the three case:

case1: VSS ≤ VIN ≤ VIL, digital input leakage current is less than 1uA.

case 2:VIL < VIN < VDD, digital input leakage current is from 3uA to 26uA

case 3:VIN = VDD, digital input leakage current is less than 1uA.

But data sheet does not list the case: VIH<Vin<VDD, I suspect that the digital input leakage current is also less than 1uA in the case.

when VIL<Vin<VIH, the digital input leakage current will range from 3uA to 26uA, as the data sheet says.

Note that VIL=0.35*VDD=1.15V, VIH=0.75*VDD=2.4V when the VDD is 3.3V.

I have asked the test team for help, maybe they can test and give the spec.

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Contributor II

Is there any news on this?  As mentioned either the data sheet is wrong (or at least unrealistic) or the part has serious issues.  A definitive answer to allow worst-case design would very be appreciated.  Thanks

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Contributor IV

Hello, Ian!

I see this topic is nearly 3 years old. Did you ever get a satisfactory answer? Did you work it out yourself some other way?

I am confronting the same issue, as I have a voltage divider in front of my digital inputs, lowering automotive voltages down to something the micro can survive (I am using a K10, but the data sheets are identical). The customer requires this network to have a high impedance and if the digital inputs can really bleed 49 µA into my divider, they can hold the input voltage the micro sees above V[IL] even when the customer shorts the input to ground!

I also cannot follow xiangjun.rong's explanation, as the input to a CMOS inverter should be a pair of FET gates. If you bias them between V[IL] and V[IH] non-negligible current will flow from V[DD] to ground, but it should not flow around the transistor and out the gate terminals. (A schematic fragment would help here.)

As it stands I can't see any solution short of placing buffers in front of the micro inputs. What did you do?

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Contributor IV

For anyone who tunes into this channel 3 years from now, NXP has confirmed that the 49 µA next to V[IL] < V[IN] < V[DD] when V[DD] = 3.0 V is a typo and should be 19 µA.  Also told me the leakage comes mostly from circuitry added to the inputs so they can tolerate 5 V.