K22 I2S 2-channel DMA operation

[scottm]

I'm currently using an I2S TX channel in DMA mode on a K22FN1M0 with the Processor Expert component in CW 10.7.  It works fine with a single TX channel and I've been running it that way for several months with no trouble.

Now, I'm trying to set up a second TX channel.  I'm using the SendBlocks() method and for testing I have both channels pointed to the same data buffer.  If I have DMA disabled, it works fine.  I get all of my data out, and I get exactly the same thing on both channels.

If I set it to use DMA, things get weird.  The channels get out of sync and one finishes in half the time of the other.  The second channel seems to be dropping a lot of data.

Has anyone run this configuration before?  I've spent most of my morning tinkering with it but haven't dug deep into the generated code yet.  The rest of my afternoon is full of meetings so I figured I'd ask here.

Note that this is not actually running I2S or any closely-related protocol.  Each channel is emulating a 1-wire protocol.  The clock and framing signals aren't used at all.  I'm just using the channels as shift registers.

Thanks,

Scott

[isaacavila]

Hello Scott,

How are you? I'd like to know if you are using same DMA's source trigger (in this case, I2S TX trigger) to generate the trigger signal for both DMA channels (TCD)? In this the case you are facing?

If so, then, there is a note in the reference manual that talks about avoid to use the same source trigger for two or more channels (eventhough one channel is disabled) because it can result on an unpredicted behavior:

This note is taken from Channel configuration register (DMAMUX_CHCFGn) in DMAMUX chapter.

That would explain the fact that this error is not presented when DMA is disabled.

As a workaound, you can try to use two linked channels to move data to I2S TX, however, this data will won't be synchronized and channel 2 needs to wait until channel 1 has finished.

I hope this can help you!

Best Regards,

Isaac

[scottm]

Hi Isaac,

I'm looking at the generated code for the two DMA channel components and yes, it looks like they're both set to the same source, the I2S transmit DMA request.

The I2S component seems to suggest that the dual-channel DMA configuration is supported. It doesn't give any warnings, and it dutifully creates two DMA channel components.

I don't see any obvious way to change the DMA configuration from within Processor Expert.  That's why I took my question here first - often PEx just doesn't do something, and if it's a known limitation I don't want to be wasting my time trying to debug the PEx code.

Perfect synchronization between the channels isn't required - up to 1 ms of offset would probably be acceptable - but the two channels do need to run at close to 100% capacity. The whole point of adding the second channel is to get data out faster.

Is there supposed to be a way to do DMA to both channels?  Seems like a major limitation if it can only handle one.

Thanks,

Scott