Yes, 50MHz for 'bursts' can be output by the CPU at '100% busy', (and presumably 60MHz from 120MHz CPU/60MHz bus) but more to the point a bit-bang SPI requires 'code that does stuff' in a loop (or even unrolled), as I created in:
Confirming K22F Clock Frequency
I doubt you will get much better than 15 clocks per loop, or 8Mbits/s from 120MHz cpu for a bit-banged SPI.
Now of course that all assumes you need to stream in/out 'general' data, and strobe with a clock -- presumably with some 'time' between edges of data and clock. IF you have 'more flash space than time' and ONLY want to 'send', I could envision 256 'output sequence routines', one for each possible byte-pattern of your data, and each would be a simple sequence of 'toggle I/O' instructions that will dither the I/O lines in the necessary order. IF the clock and data can change at the same time (from one instruction) on one of the clock edges, then I could indeed see where each byte could 'burst' out at the full 50/60MHz, but then plus a little 'overhead' to decode the next byte on a 'computed GOTO' (switch).