Is the Reset Line Required to be pulled low when attempting a Mass Erase over SWD.

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Is the Reset Line Required to be pulled low when attempting a Mass Erase over SWD.

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leejones
Contributor I

I am attempting to perform a Mass Erase operation on a secured MK20DX256VLH7. 

When not secured, the device Erases fine.

When secured, the "Flash Mass Erase Acknowledge" bit is never set. 

In some documentation "Production Flash Programming - Best Practices for Kinetis K- and L- Series MCUs", it suggest asserting the Reset pin, it also mentions, that should there not be a Reset pin connected, it can be done by setting the 'System Reset Request' bit in the MDM-AP register. However..... in the Data Sheet, its says this bit cannot be set while in secure mode......

Am I correct in assuming that to Mass Erase a Secured MK20DX256VLH7, I must hold this pin low?

Or is there another way?

Thanks

Lee

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Lee Jones,

     I also received your question from the service request, and I already reply you about this question.

    If you still enable the mass erase, you can use the JLINK commander with unlock kinetis to unsecure the chip.
   But if you disable the mass erase, and secure it, then chip can't be unsecured.
Is your timeout when do unlocking from JLINK?
If yes, it is really a problem, maybe your mass erase bit is really disabled, this situation is secured to the highest level, can't be unsecured.
About security, you can refer to this document:
https://community.nxp.com/servlet/JiveServlet/download/857127-1-396709/Kinetis%20Lock%20issue%20anal...


Besides, please also take care of the nearby RF source, I encouter a customer put the board near to the WIFI source, then the SWCLK and the SWDIO have a 2.4GHz 1.7V voltage, it damaged the SWD port.

  About the reset pin, you can try to hold the reset pin low, then unlock the kinetis. If the chip SWD port is not broken, or the chip mass erased is not disabled, it should be unsecured by hold the reset pin low.


Have a great day,
Kerry

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