Hello Santosh
Try adding this line in your code:
test_tcd->CSR |= DMA_CSR_DREQ_MASK;
DREQ[CSR] bit clears automatically ERQ flag when the transference is done (current major iteration count reaches zero), therefore is not necessary clear by software.
About your other question, yes it's possible. DMA_TCDn_DLASTSGA can apply to restore the destination address to the initial value at the completion of the major iteration count. This register allows signed writing, for example, if you need to fill in a Buff[10] and reload with new values at the completion of the major iteration, write DMA_TCDn_DLASTSGA = -10 to return from &Buff[9] direction to &Buff[0].
I hope you succeed.
Regards.