I2S/SAI audio clock setting

[eddiec]

Hello All,

We build an platform by using TWR-K60F120M(Rev.C ) with my own CODEC board, connected with wire from TWR's female header A21~A25( I2S signal and clock), my system are CW10.5 and MQX4.0.0.

I test the "i2s_demo" under "mqx" subfolder, insert a microSD card including a 48kHz/24bit stereo wav file then download the project. when I type play command on shell, I can see the wav file is playing well on console( there are some error message stop on "initial_codec" and "setup_codec", so I commented them out to pass it), but the clock signal are not correct. so I change "CLK_MULT" from 384 to 256 then I could measure that MCLK = 12.288MHz and BCLK = 3.072MHz( system use EXTAL_MAIN 50MHZ by default, jumper J18 on and J6 off), that's what I need but LRCK is 64kHz, it's very weird because I had checked the wav file header and played by some audio player, the sample rate is 48kHz, but sample rate on shell message is 51200Hz, and 64000Hz on LRCK pin as I mentioned earlier.

So I surveyed AN4520 and AN4800 which document explain about I2S application on Kinetis, the chapter 3.1 have some key words like I2SSRC, but I can't found any clue on K60P144M150SF3RM.pdf, even SIM_SOPTx didn't have any register about I2S/SAI.

We would like to know how to control I2S signal including:

1. 3 clocks(MCLK' BCLK and LRCK).

2. 2 data(DIN' DOUT)'s from PTA to PTE.

3. Change clock source from 50MHz(Y1) to 12MHz(Y5) and use it.

Any help will be appreciated!

Kind regards,

Eddie

[madalinastanca]

Hi ,

I try to understand the i2s demo application and I have some questions if you can help me:

1. Where are audio frames read from SD card?

2.How is realised the sync in real time?

3.How are the   frames transfered to the codec?

4.How is realised the synchronize  with the  playing flow?

Thx!

[eddiec]

Dear Madalina,

Thanks for your participation! please see my answer below:

1. About the audio frame you said, I think it's setting in the system, you can find "header.FMT_SUBCHUNK.SampleRate" in sh_audio.c, which including a Sample Rate( audio frame?)'s information of wav(RIFF) header file .

2 & 4. I use logic analyzers to measure whole signal line simultaneously, I can see the clock is accurate but not I want in 48k/24bit( I need 48kHz of LRCK but not 64kHz), the sound quality sounds no problem in 48k/16bit .

3. By connected with wire from TWR's female header A21~A25( I2S signal and clock).

Kind regards,

Eddie

[likong · Accepted solution]

Hi, Eddie

I2S and SAI is different audio IP. In K60F120, it is SAI. I think the pdf version may be wrong, I have the same pdf(K60P144M150SF3RM.pdf) and I can find SAI...

For your question,

1. MCLK = LRCLK * CLK_MULT, also it is divided by MDR register. MCLK = ClockSorceFeq * (MDR[FRACT] + 1)/(MDR[DIVIDE] + 1)

BCLK = MCLK/((TCR2[DIV] + 1) *2)

2. You just need to re-configure the pin mux for the SAI. In MQX, change the function _bsp_sai_io_init(),in mqx\source\bsp\twrk60f120m\init_gpio.c

3. If changed in MQX, in mqx\source\bsp\twrk60f120m\init_sai.c, change the clock source in the structure. If you want to change in registers, change the MCR[MICS] bit, the meaning of each choice can be found in chip configuration chapter of the reference manual.

[eddiec]

Dear Li,

Thanks for your kindly reply, I have found an Application Note AN4526 which says the I2SSRC have moved to I2Sx_MDR.

1. About the code you said in i2s_demo are:

mclk_freq = header.FMT_SUBCHUNK.SampleRate * CLK_MULT;

The sample rate is come from wav file's header(48kHz), I think it's OK because the MCLK I measured is 12.288MHz, but I can't found the actual setting of register like this one( under sai_int_ksai.c):

     static uint_32 _ki2s_get_mclk_value

     (

        KSAI_INFO_STRUCT_PTR io_info_ptr

     )

     {

         I2S_MemMapPtr i2s_ptr = io_info_ptr->SAI_PTR;

         uint_32 freq = _bsp_get_clock(_bsp_get_clock_configuration(), io_info_ptr->MCLK_SRC);

         uint_32 fract = 0;

         uint_32 div = 0;

         fract = (i2s_ptr->MDR & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT;

         div = (i2s_ptr->MDR & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT;

         return ((freq / (div + 1)) * (fract + 1));

     }

It's looks like the formula to get MCLK, when I search "I2S_MDR_FRACT_MASK" or "I2S_MDR_FRACT_SHIFT", it doesn't exist in another code, where can I check the value they are?

2. This code is very clear to know each pin's function, I can realize the literal meaning and replicability, but I would like to know more details of each variables setting like question.1, I can't find more relevant code about it, example:

PORTA_PCR13 |= (PORT_PCR_MUX(0x06) | PORT_PCR_DSE_MASK);

I can't search another result about setting on "PORTA_PCR13", "PORT_PCR_MUX" or "PORT_PCR_DSE_MASK".

3. I'll try to adjust it by registers, there's some relevant setting code in bsp_cm.c & bsp_cm.h, I think changing both I2S and system clock is what I need!

4. An additional question is about i2s_demo in MQX.

When I played a sound file A.wav(48kHz/16bit-stereo), the I2S clock are MCLK = 12.288MHz' SCLK = 1.536MHz' LRCK = 48kHz, and playback information on shell displays 48000Hz, it plays no problem; but when I play a sound file B.wav(48kHz/24bit-stereo), the I2S clock are MCLK = 12.288MHz' SCLK = 3.072MHz' LRCK = 64kHz, and playback information on shell displays 51200Hz, it's very strange because 1536/48 is not equal to 3072/64, It's hard to realize how system can get these value, especially 51200 on shell.

If you can give me some suggestion to find how it works, that would be grateful!

With regards,

Eddie

[likong]

Hi, Eddie

For your question 4, in MQX 4.0, it may be a bug...I think maybe the 24-bit audio is not well supported.

[eddiec]

Dear Li,

I have found the real value of question 1'2, they are in psp -> Cortex -> MK60F15.h, it's a huge header file which including many parameters!

Thanks~

Best regards,

Eddie