I2C without ODE enable, 0.4V

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I2C without ODE enable, 0.4V

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daweiyou
NXP Employee
NXP Employee

Hi:

I meet same problem with below link.

Kinetis I2C ODE

when ODE bit is not enable in PCR register, the low voltage (0V expected) from slave device is 0.3V instead,

I know now is pull-push structure, but how the 0.3v generated? and input and output circuit is same one or disconnected when operating the other?

thx.

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perlam_i_au
Senior Contributor I

Hello Dawei:

I take a look on the thread you mention and for this case I would like to know what part number are you using? Also I would like to see your port configuration code, could you please share it?

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daweiyou
NXP Employee
NXP Employee

Hi Perla:

The partnumber is K60DN512VLQ10, and MQX 3.8 default has ODE enable, for some special case, remove this bit, can see above issue;

And for Kinetis 100M bare mental code, the I2C sampel also has ODE cleared.

thx!

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mjbcswitzerland
Specialist V

Hi

The I2C functional description in the K60 manual states that all devices connected to the I2C bus MUST have open drain (or open collector) outputs (in accordance with standard I2C specification).

If there is SW being used that doesn't set the used pins to open drain there is an error in the SW involved and this needs to be corrected (wherever the SW is derived from and whether the SW is "expected" to be correct or not).

When this is not respected the voltage measured will depend on the drive strengths of the connected devices (one may be trying to drive '0' and another trying to drive '1') and so the voltage will be somewhere between the two (with potentially quite high currents flowing). What the measured voltage actually is is not really that relevent because it is a product of a SW error which needs to be addressed.

In case of the KL parts it is different since the output is automatically set to pseudo-open-drain mode when the I2C pin functions are selected. This means that the SW can't actually make a mistake in relation to the output drive configuration.

Regards

Mark

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daweiyou
NXP Employee
NXP Employee

Thx Mark.

The issue is caused by SW clearly, but for my customer they make mistake to add 100pF capacitance on bus, and they have no chance to change HW.

So for wrong circuit, if ODE is enable, glitch will occur, which is caused by capacitance; if ODE disabled, the wave is OK, but device can't drive to 0 voltage, only 0.4V.

BTW, only one device on bus.

So I want to know the risk, whether the ODE bit disable is allowed or possible.thx!

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mjbcswitzerland
Specialist V

Dawei

I would not expect 100pF to cause any problems. The I2C bus is specified to operate with up to 400pF - I2C Bus Range and Electrical Specifications, Freescale 9S12 HCS12 MC9S12 I2C Hardware and adding small capacitors to the signal lines is used to improve interference immunity.

In addition to that I don't see how open-drain outputs cause glitches to occur. Since they switch only to '0' and not to logic '1' there should be slightly less "glitching" if anything.

Therefore I recommend that you do an electrical analysis of your hardware to identify how a glitch is possible.

Regards

Mark

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daweiyou
NXP Employee
NXP Employee

Got, thx Mark for your remainding.

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