I2C problem using DMA on K66

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I2C problem using DMA on K66

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emanuelemarracc
Contributor II

Dear All,

I'm using Kinetis K66 processor (MK66FN2M0VMD18) on a custom board and I'm having some troubles when I'm using DMA for I2C and SPI peripherals.

I'm using the following configuration:

- I2C0 peripheral on DMA channels 0 and 1;

- SPI0 peripheral on DMA channels 4 and 5.

When the SPI DMA channels are used it seems that I2C DMA channels stop wornking correctly. Notice that I2C DMA channels work fine until the SPI starts.

I've done a lot of tests and it seems that the problem is the DMA configuration or something like that.

If I switch DMA channel configuration priority like this the problem disappears but I don't know why:

- I2C0 peripheral on DMA channels 11 and 12;

- SPI0 peripheral on DMA channels 4 and 5.

Have you ever had a similar behavior? Could You explain the reason for the resolution of the issue when I change the priprity orde? Is this the correct way to operate or not?

Thank You for Your support, I will appreciate any answer or concerning experience about this issue.

Best regards

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FelipeGarcia
NXP Employee
NXP Employee

Hello Emanuele,

 

This seems to be an issue with the DMA channels priorities. If the priority in the SPI channels is higher and the baud rate is higher as well, then the I2C channels won't have time to be executed.

 

That's why I2C channels worked at first, but when SPI transmissions starts then I2C stopped working.

 

Hope it helps!


Have a great day,
Felipe

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1,127 Views
emanuelemarracc
Contributor II

Dear Felipe,

Thank You For Yor Answer!

You say that

If the priority in the SPI channels is higher and the baud rate is higher as well, then the I2C channels won't have time to be executed.

You mean that if the channel with lower priority is executing and it is interrupted by the higher priority channel, it never continue executing?

When an higher priority channel interrupts the lower priority, the latter stops or is definitely terminated? Does the lower priority channel continue its execution after the higher priority channel execution ends? Or is it terminated and never continue its execution?

Please note we're using SPI channel at 1.25Mbit/s and I2C channel at 370Kbit/s.

What is the right way to operate? Could You show me where to find these information on official documents and papers?

Thank You for Your answer.

Best Regards

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FelipeGarcia
NXP Employee
NXP Employee

Hi Emanuele,

 

Sorry for my late reply.

 

I recommend you to check chapter 7.1.2.3 of the Kinetis Peripheral Module Quick Reference.

https://cache.freescale.com/files/32bit/doc/quick_ref_guide/KQRUG.pdf

Hope it helps!

Have a great day,
Felipe

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emanuelemarracc
Contributor II

Dear Felipe,

thank You for Your reply.

I've checked chapter 7.1.2.3 of the Kinetis Peripheral Module Quick Reference. The documents reports this description:

In the fixed priority scheme each channel is assigned a priority level. When multiple requests are pending, the channel with the highest priority level performs its transfer first.By default, fixed priority arbitration is implemented with each channel being assigned apriority level equal to its channel number. Higher priority channels can preempt lower priority channels. Preemption occurs when a channel is performing a transfer while atransfer request is asserted to a channel of a higher priority. The lower priority channel halts its transfer on completion of the current read/write operation and allows the channel of higher priority to work.

My question is:

- Does the lower priority channel continue its transfer after it has been interrupted by an higher priority channel, when the latter has completed its work?

- Or does the lower priority channel ends its transfer when it has been interrupted and I need to start a new trasmission?

The Kinetis Peripheral Module Quick Reference seems to say nothing about this issue.

Thank You for Your answer.

 

Best Regards

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FelipeGarcia
NXP Employee
NXP Employee

Hi Emanuele,

 

This is mentioned in the last part of the paragraph you copied.

The lower priority channel halts its transfer on completion of the current read/write operation and allows the channel of higher priority to work.

In other words, the lower priority channel continue its transfer after it has been interrupted by an higher priority channel.

 

Best regards,

Felipe

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