How to determine when SPI trnsaction completed

[pgo]

Hi All,

I am using the PCS signals on the SPI interface on a Kinetis device (MK20 or MK64).

The signal correctly changes so that's not a problem.

But... how do you determine when the entire transaction has completed i.e. when the PCS signals has returned to its idle state?

The SR.TCF bit only indicates that the last bit has been shifted out.  This (obviously) occurs before the PCS signal returns to idle.

I had thought the SR.TXRXS signal might be useful but it doesn't seem to be the case.

Currently I'm polling the PCS signal through the port PDIR register but this is less than elegant - It requires custom code depending on which pin the PCS is mapped to.

Any suggestions?

Thanks

[mjbcswitzerland]

Hi

I don't know whether it is possible to "see" when the automatic Chip select control has negated the CS line after sending the final byte of data (apart from monitoring the state of the pin). However if I were doing it (and didn't find a better method) I would consider controlling the CS line in SW as a GPIO instead of automatically (unless there is some special timing performed by the automatic mode). Then you could monitor the RX flag which indicates that the last Rx bit has been clocked in (even if no rx is used) and then negate the CS manually. You would at least know exactly when the CS line negates.

Regards

Mark

[pgo]

Hi Mark,

Yes using a manual approach on the CS bit would work fine but it has the same problem as the method I'm using - namely that there is extra code that has to know about which port pin is being used.

Not a big deal but the automatic PCS function is useful and I was hoping for an  "elegant solution".  (For some arbitrary, possibly unrealistic, level of elegant :smileyhappy:.)

I'm just re-reading the discussion of operating mode for the SPI and there is some information there that might mean that I could use the SR.TXRXS bits if I set thing up correctly.

I'll have a play with this a post any progress.

bye

[adriancano]

Hi,

When you transfer data you need to write to the PUSHR which looks like this:

It has 2 bytes of command and 2 bytes of data; every time you transfer you need to write completely to this register and when you write your last data you need to set the EOQ bit.

You can check for this bit in the SPIx_SR register and also check for the TFFF flag which indicates that the TX fifo is full. You can implement this with this code:

    while(!(SPI0_SR & SPI_SR_TFFF_MASK)) {} //wait till TX fifo not full

    while(!(SPI0_SR & SPI_SR_EOQF_MASK)) {} //wait till the las entry has been transmitted

    SPI0_SR  |= SPI_SR_EOQF_MASK; //clear EOQF flag

    SPI0_SR     |= SPI_SR_TFFF_MASK; //clear TFFF flag

This when you are transmitting data.

I hope this information can help you.

Regards,

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. It would be nice!

-----------------------------------------------------------------------------------------------------------------------

[pgo]

Hi Adrian,

I don't believe the approach you suggested would indicate that the CS bit has been negated.  It would effectively wait for the transmission to complete which is earlier i.e. when the last bit has been clocked out..  However I will spend some time checking this.

Thanks for the suggestion.

bye