How to activate K60´s 2nd Channel of Flex Timer FTM2 for PWM unter Keil

[tfrauenrath]

Hello,

a was able to configure a PWM on the first channel of the FTM2 port on a K60. How can I activate also

the 2nd channel on Pin B19 without influencing with Pin B18?

This is my working code for channel one. Unfortunately there is no "FTM_C0SC_MSB_MASK" or

"FTM_C1SC_MSB_MASK" as example. In "MK60N512MD100.h" there is only "FTM_CnSC_MSB_MASK".

Thank you!

This is the .h file provided by keil:

http://www.keil.com/dd/docs/arm/freescale/k60/mk60n512md100.h

This is my working code for channel 0:

/*-----------------------------------------------------------------------------
* DA_init: Initilizes digital to analog PWM engine
*
* Parameters: (value, channel)
* Return: (none)
*----------------------------------------------------------------------------*/

void DA_init (void) {
/*Enable the Clock to the FTM0 Module*/
SIM->SCGC3 |= SIM_SCGC3_FTM2_MASK; 

/*Pin control Register (MUX allowing user to route the desired signal to the pin. */
PORTB->PCR[18] = PORT_PCR_MUX(0x3); 
PORTB->PCR[19] = PORT_PCR_MUX(0x3); 

/*When write protection is enabled (WPDIS = 0), write protected bits cannot be written. When
write
protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the
negation of
the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as
a 1
and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect.*/
FTM2->MODE |= FTM_MODE_WPDIS_MASK;

/*FTM Disable; Only the TPM-compatible registers (first set of registers) can be used without
any restriction. Do not
use the FTM-specific registers.*/
FTM2->MODE &=~FTM_MODE_FTMEN_MASK;


/*Quadrature Decoder mode is disabled.*/
FTM2->QDCTRL &=~FTM_QDCTRL_QUADEN_MASK; 

FTM2->CNT = 0; /*16bit - FTM Counter Value - reset counter to zero*/
FTM2->MOD = 65534; /*Overflow rate; The Modulo register contains the modulo value for the
FTM counter.*/
FTM2->CNTIN = 0; /*Set the Counter Initial Value to 0*/

// // FTMx_CnSC - contains the channel-interrupt status flag control bits
FTM2->CONTROLS->CnSC |= FTM_CnSC_ELSB_MASK; FTM2->CONTROLS->CnSC &=
~FTM_CnSC_ELSA_MASK; /*Capture on Falling Edge Only*/
FTM2->CONTROLS->CnSC |= FTM_CnSC_MSB_MASK; //Channel Mode select

//Status and Control bits
FTM2->SC = FTM_SC_CLKS(0x01); // Selects Clock source to be "system clock" or (01)
//sets pre-scale value
FTM2->SC |= FTM_SC_PS(0x08);

/*activate output*/
FTM2->CONTROLS->CnV = 400;
}

[paulmartin · Accepted solution]

Your code only has one mistake with the CONTROLS registers

You need to specify an array index CONTROLS[i].

In your code the value i = 0. That is why you will always change your channel 0 settings when trying to configure channel 1.

This is how I configure 3 PWMs:

FTM0->CONTROLS[0].CnSC = 0x00000028; /* channel configured for edge aligned PWM */

FTM0->CONTROLS[1].CnSC = 0x00000028; /* channel configured for edge aligned PWM */

FTM0->CONTROLS[2].CnSC = 0x00000028; /* channel configured for edge aligned PWM */

FTM0->CONTROLS[0].CnV = 6249; /* start PWM with 100 % duty cycle */

FTM0->CONTROLS[1].CnV = 6249; /* start PWM with 100 % duty cycle */

FTM0->CONTROLS[2].CnV = 6249; /* start PWM with 100 % duty cycle */

You can use the named masks instead of explicit values in CnSC.