How can I refresh KEA SPI data register for transmitting?

[fortunely]

Hi NXP Team,

We are developing a sensor just like KMA210, using S9KEAZN8AMFK as 24bit-SPI slave.

Time between SPI master CS low and CLK first rising clock is too short, about 4~5us. 

I find out it takes about 2us from CS falling edge to software capture the edge using FTM capture(and GPO output high level in FTM interrupt function). If I write one data to SPI0_D after CS low, it may not have enough time to transmit the writing data and send out wrong byte order.

So, I write one byte data to SPI0_D register before CS low. But it results in another problem, that is, I can not refresh the SPI0_D after writing it except completing one byte transmitting. If I have write one byte to SPI0_D, it would be out of date in several minutes later.

How can I refresh KEA SPI data register(SPI0_D) for transmitting?

[kerryzhou]

Hi Martin Zhang ,

    Thank you for your interest in NXP kinetis product, I would like to provide service for you.

  1. What's the master your are using?

     Maybe you also can consider to increase the time between the CS low and the SCK rising.

  2. refresh the SPI0_D

     Could you give me more details? Do you mean, when you write one byte data to SPI0_D, but you don't want to send it, want to refresh it? If yes, this should be the code side problem.

    By the way, how do you write the data register? Do you wait the S[SPTEF] is set?

The S register must be read when S[SPTEF] is set before writing to the SPI data register; otherwise, the write is ignored.

Any updated information from your side, please kindly let me know.
Have a great day,
Kerry

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[duffytang]

Q1:

  1. What's the master your are using?

     Maybe you also can consider to increase the time between the CS low and the SCK rising

A1:

Our product act as slave.  We can't change the time between the CS low and the SCK rising.So,the time  between the CS low and the SCK rising just is 4-5us.

Products Requriment:

A brief description：When CS is enabled, SPID transmits real-time ADC data.

Our implementation methods and problems encountered：

(1)First method:

Before CS comes, ADC is collected continuously, and SPI-D is updated every time ADC is collected.

Question:

When the SPID is not empty, new data cannot be written to the SPID.

(1)Second method:

Before CS comes, ADC is collected continuously, and SPI-D is updated when the cs is enable.

Question:

CS low and the SCK rising is so short cause the fault data.

[kerryzhou]

Hello,

Hi duffy tang,

   OK, thank you for your updated information.

  Could you tell me what the core clock you are using? the core frequency.

  Could you also share SPI_D data write code with me?

  I need to check some code clock. It's better to use the register to control it directly, just to save code execute time.

Have a great day,
Kerry

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