Freedom Board 8 Mhz to 48Mhz MCG setup code.

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Freedom Board 8 Mhz to 48Mhz MCG setup code.

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JimDon
Senior Contributor III

Code to set the Freedom Board MCG to 48MHz.

/*

* init_clocks()

* Set the PLL to 48MUz from the 8Mz xtal on the

* Freedom board.

* Returns:

* The freequency set from the divide/multiply register values.

*/

int  init_clocks()

{

    signed char prdiv; signed char vdiv;

    // Set the core/system clock to divide by 2.

    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1);

    // 12.2.3 Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral

    // clocking options.

    SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;

    // 12.2.1 Set OSC32KSEL to 00 to select the System oscillator

    SIM_SOPT1 &= ~(SIM_SOPT1_OSC32KSEL(3));

    // Select MCGFLLCLK clock or MCGPLLCLK/2 fpr TPM

    SIM_SOPT2 &=  ~SIM_SOPT2_TPMSRC(3);

    SIM_SOPT2 |=  SIM_SOPT2_TPMSRC(1);

  

    // Set up for external XTAL. 10.3.1 KL25 Signal Multiplexing and Pin Assignments

    // Set pin function to EXTAL - Clear to 0 (pin 40)

    PORTA_PCR18 &= ~(PORT_PCR_ISF_MASK | PORT_PCR_MUX(7));                                                

    // Set pin function to XTAL -  Clear to 0

    PORTA_PCR19 &= ~(PORT_PCR_ISF_MASK | PORT_PCR_MUX(7));

    // FBE Mode

    OSC0_CR = OSC_CR_ERCLKEN_MASK;                                                

    MCG_C2 = (MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK);                                                

    MCG_C1 = (MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK);                                                

    MCG_C4 &= ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(3));                                                

    MCG_C5 = MCG_C5_PRDIV0(3);                                                

    MCG_C6 = 0x00U;  

    // Wait for FLL extern ref.

    while((MCG_S & MCG_S_IREFST_MASK) != 0)

      ;

    // Wait for external ref. select.

    while((MCG_S & MCG_S_CLKST_MASK) != 8)

      ;

    // PBE

    MCG_C2 = (MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK);                                                

                                              

    MCG_C6 = MCG_C6_PLLS_MASK;

  

    // Wait for lock.

    while((MCG_S & MCG_S_LOCK0_MASK) == 0)

      ;

  

    // PEE Mode

                                              

    MCG_C1 = (MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK);                                                

  

    // Wait for PLL select.

    while((MCG_S &MCG_S_CLKST_MASK) !=MCG_S_CLKST_MASK)

      ;

    // Use actual PLL settings to calculate PLL frequency

    prdiv = ((MCG_C5 & MCG_C5_PRDIV0_MASK) + 1);

    vdiv = ((MCG_C6 & MCG_C6_VDIV0_MASK) + 24);

    return ((8000000 / prdiv) * vdiv);

}

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JimDon
Senior Contributor III

Find file with code attached.

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