FlexBus Chip Selects Not Routed To Pins

[gcary]

I'm having difficulty squeezing in all of the peripherals I need into a K60 design.  I am using the FlexBus, which consumes a lot of pins.  I'm down to just a couple of pins that have conflicting assignments.  Do FlexBus chip selects need to be routed to a pin?  I don't need a chip select pin because the FlexBus is interfacing to an FPGA.  The FPGA will decode the address and know how to behave, so it doesn't need the chip select.  I need 2 chip selects because I will have two functions in the FPGA and each will have different timings.  Chip selects control a number of FlexBus parameters, such as wait states, port size, Byte-lane shift, etc.

Please correct me if I'm wrong about not needing the chip select signal.  ALE signifies the start of a cycle.  After one word is written in a write cycle, the FPGA will end the cycle internally and begin look for ALE to be asserted again.  For read cycles, the OE_n signal has the same timing as the chip select.  So no chip select is needed for reading or writing. All of the transfers will be single-word.

Thanks,

Greg

[xiangjun_rong]

Hi, Gcary,

sorry for the delay.

Regarding your question, pls refer to the section 4.2 System memory map in K60 reference manual.

0x6000_0000–0x6FFF_FFFF Flexbus (External memory - Write-back) All masters S4

0x9000_0000–0x9FFF_FFFF FlexBus (External memory - Write-through) All masters S4

0xA000_0000–0xDFFF_FFFF FlexBus (External peripheral - not executable) All masters S4

If you access the above space, the FlexBUS will generate the signals to access external memory.

[xiangjun_rong]

Hi, Gcary,

whether you need to connect the /CSx signal to FPGA is dependent on the address connection, I think it is necessary to connect the /CS pin to FPGA.

After you connect the /CS pin, you are not required to connect all 32 address pins to FPGA, for example, assume that the FPGA includes 256 Bytes, in the case, you just connect the FB_A0~FB_A7 address and one /CSx, it is okay, the High address from A8~A31 are not required to be connected. If you do not connect /CSx, you have to use High address to decode the chip select by FPGA itself, obviously, you need more high address pins besides the FB_A0~A7 pins. There is a FB_CSARn register of FlexBUS, which can specify the high address.

Regarding the FB_ALE, in order to reduce the FlexBUS pins number, some data and address pins are multiplexed, when the FB-ALE is high, the pins are address pins, user have to use a latch to lock the address for example 74HC373, you can make the FPGA as a latch.  when the FB_ALE is low, the pins are data bus.

Hope it can help you.

[gcary]

Hi Xiangjun,

Thank you for your reply to my question.  I think I understand what you are saying.  If I don't decode all of the high-order address lines, it is possible that the FPGA might think it is being addressed when in fact it was another address.

I was assuming that the only addresses on the FlexBus were ones meant for the FlexBus.  I still think that is probably true for security reasons.  Addresses for internal flash memory or SRAM accesses should not be visible on the FlexBus, otherwise a hacker could gain knowledge about what is going on inside of the chip.

The FPGA will only look at addresses when ALE is high.  You are correct I will not be decoding all 32 address lines.  Do you know if the FlexBus ever drives ALE and addresses not meant for the FlexBus?

Thanks and regards,

Greg