FFT Metering on Cortex-M4

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FFT Metering on Cortex-M4

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sbranover
Contributor I

Is there any information about the function performance for the FFT-Based Metering Algorithms using the Cortex-M4?

AN4255 only has info for CM0+ and CM0+ with MMAU.

It seems to me that the performance is far worse on the M4 than on the M0+ with MMAU. 

Most noticeably the following functions seem to be taking a long time:

METERLIBFFT3PH_GetMagnitudesPh

METERLIBFFT3PH_GetPhasesPh

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Shmuel,

As you know that we use Kinetis KM family in the energy metering application, the KM family integrates PGA, SAR-ADC, AFE ADC, so almost all application notes and reference code are based on Cortex-M0 plus, because KM family use Cortex-M0 plus as core. Unfortunately, we have not the doc which compares the performance difference between cortex-M0 and cortex-M4 core. But the cortex-M4 has higher performance especially FFT, beacuse the cortex-M4 have a lot of single cycle computation assembly instructions, but it is depemdent on the assembly instructions of api function which executes.

Hope it can help you

B R

xiangjun rong

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sbranover
Contributor I

Thanks for the response.

Do you know if the FFT metering library makes use of the optimizations available on the Cortex-M4? As the library is supplied without the source code it is hard to tell without going through the disassembly.

Measuring performance time with an oscilloscope it seems that the library takes longer (almost 2 x clock cycles) on the CM4 compared to the CM0+ with MMAU.

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MarMi
NXP Employee
NXP Employee

Hi Shmuel,

please refer to fraclib_inlines.h and fraclib.h header files in FFT library installation folder for information regarding math type used in library for different core platforms.

There are two defines in fraclib_inlines.h:

  • #define USE_MMAU
  • #define USE_FRACLIB_MUL32

Those defines were used as follows:

  • Library for CM0+ core w/o MMAU:  math code base compiled with define USE_FRACLIB_MUL32
  • Library for CM0+ core w/ MMAU:  math code base compiled with define USE_MMAU
  • Library for CM4:  code base compiled with none of defines

Note that faster computing of the metering algorithm with CM0+ w/ MMAU vs. CM4 is expected because instruction set of the MMAU has been tailored to the power metering use-case. Some more information available from here: FTF-SCE-F1516.pdf.   

Kind regards,

Martin M.

ludek

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sbranover
Contributor I

Thanks Martin,

It seems a floating point implementation would be best for the CM4.  

Best,

S

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Shmuel,

can you tell me  which api functions you tested? what are the core clock frequency for both Cortex-M0 and Cortex-M4 cores?

BR

Xiangjun Rong

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sbranover
Contributor I

It is the Cortex-M0 w MMAU

Signals are 64 samples 

Signals used from inputdata.h:

u1 - sin_64s_6e6_5h_10p

u2 - sin_64s_6e6_5h_10p_121deg

u3 - sin_64s_6e6_5h_10p_239deg

i1 - sin_64s_4e6_5h_40p_sh_offs

i2 - sin_64s_1e6_5h_10p

i3 - sin_64s_4e6_5h_40p_sh_offs

Core Clock Frequency:

Cortex-M0 - 71.991296 MHz

Cortex-M4 - 120.0 MHz

Running Times

METERLIBFFT3PH_CalcMain() without phase shift

Cortex-M0 - 1.97 mS

Cortex-M4 - 1.76 mS

METERLIBFFT3PH_CalcMain() with phase shift (-60.0 degrees) on all harmonics

Cortex-M0 - 2.85 mS

Cortex-M4 - 5.24 mS

The sequence:

METERLIBFFT3PH_GetMagnitudesPh1()

METERLIBFFT3PH_GetMagnitudesPh2()

METERLIBFFT3PH_GetMagnitudesPh3()

METERLIBFFT3PH_GetPhasesPh1()

METERLIBFFT3PH_GetPhasesPh2()

METERLIBFFT3PH_GetPhasesPh3()

Cortex-M0 - 0.49 mS

Cortex-M4 - 1.13 mS

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