FEE CLOCK ERROR WITH FLL

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FEE CLOCK ERROR WITH FLL

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Iotelctronic
Contributor II

I am working with an MKE06Z128VQH4 microcontroller, and I am configuring the clock frequency in MCUXpresso. I want to use FEE mode because I have a 12 MHz crystal. My board is custom-made, and I’m having problems with the configuration — mainly with the FLL, which has a constant of 1280. That value multiplies the frequency and exceeds the limit, giving me an error, and I really don’t know how to modify that constant. I’m new to using MCUXpresso.

Iotelctronic_0-1764075084293.pngIotelctronic_1-1764075265591.png

 

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Celeste_Liu
NXP Employee
NXP Employee

Hello @Iotelctronic ,

Yes, I configure the setting with the config tools. My version is v25.06. However, I think you issue is not related to the config tools version. 

Please be attention to the Frequency range when setting RDIV. You can click on RDIV in the clocks diagram on the left side of the screenshot to trigger the related settings on the right.

Celeste_Liu_0-1764813803215.png

 

RDIV can range from 32 to 1024 only when you select the high-frequency range; otherwise, as you can see, its maximum value can only be set to 128.

 

Celeste_Liu_1-1764813923826.png

 

Hope it helps.

 

BR

Celeste

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Celeste_Liu
NXP Employee
NXP Employee

Hello @Iotelctronic ,

Thanks for your post and sorry for the late response.

I have checked the Reference manual of MKE06Z128VQH4. You can see that the FLL is fixed at 1280. It cannot be modified in the Clock Config tool, which is expected and not an issue.

Celeste_Liu_0-1764744997646.png

Additionally, please refer to Table 5-5, which lists all available combinations of sources from the OSC clock for this device. As shown, in FEE mode, considering the limitation that the FLL is fixed at 1280, we recommend using an 8–10 MHz OSC with RDIV set to 256, or a 16–20 MHz OSC with RDIV set to 512.

Celeste_Liu_1-1764745559060.png

 


A 12 MHz OSC is not listed, which indicates it is not recommended. I tested both 10 MHz and 16 MHz configurations in the Clock Config Tools, and there were no issues.

Hope it helps.

BR

Celeste

 

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Iotelctronic
Contributor II

Thank you for responding. I changed the crystal to 8 MHz because I'm actually using 8 MHz as shown in the evaluation board schematic. I was confused due to a previous project with another NXP MCU that I was working on.

However, even after configuring it for 8 MHz to use FEE mode, I get an error because the RDIV divider only goes up to 128. If I divide by 128, I get an FLL of 80 MHz, which exceeds the limit. Yet, I see in the information you sent that it can be divided up to 512.

Did you configure the settings manually, or did you use the Config Tool? If you used the Config Tool, which version are you using?

Iotelctronic_0-1764762767929.png

 

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Celeste_Liu
NXP Employee
NXP Employee

Hello @Iotelctronic ,

Yes, I configure the setting with the config tools. My version is v25.06. However, I think you issue is not related to the config tools version. 

Please be attention to the Frequency range when setting RDIV. You can click on RDIV in the clocks diagram on the left side of the screenshot to trigger the related settings on the right.

Celeste_Liu_0-1764813803215.png

 

RDIV can range from 32 to 1024 only when you select the high-frequency range; otherwise, as you can see, its maximum value can only be set to 128.

 

Celeste_Liu_1-1764813923826.png

 

Hope it helps.

 

BR

Celeste

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Iotelctronic
Contributor II

Hello, I set up the clock correctly as you told me in the MCUXpresso tool and it worked well, thank you very much.

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