Hi,
I'm using a KV5x SoC for its DSP capabilities.
Mainly I'm using the PWM.
I use the EXT_SYNC signal to generate a FORCE_OUT on PWM0 sub-modules 1 and 2. (sub-module 0 uses local sync), thus changing their outputs at the same, but variable instant (but with different dead-times)
The EXT_SYNC originating from an AND of a external comparator and from PWM1 peripheral output trigger.
Until know working fine.
However, in some cases I experience a problem: it very much seems that sub-module 2 receives that EXT_SYNC signal, generating FORCE_OUT, but sub-module 1 not!
So, my (generic) question is, is that even possible? Once the signal is put on the cross-bar by the AOI-Module, then going to the AHBP/AIPS, both requesting sub-modules of PWM0 should receive that EXT_SYNC signal, or not?? Or is there any chance of a phase-shift/delay in "sampling" that signal for each sub-module? As one can see, I'm not completely understanding how that signal gets from one peripheral to another.
In order to debug this issue, I output the signal coming from the AOI-module to a XB_OUT pin.
Comparing two cases, were in one case both sub-modules receive the EXT_SYNC and thus generate a FORCE_OUT event, and in the other case, were only sub-module 2 responds, the only difference I can see is that the signal at the XB_OUT pin in case of correct behavior is about (40ns pulse-length and 1.3V peak) and in case of failure is even more narrow (about 10ns and 0.8V peak).
As the configuration is very complex, I do not expect someone to go deep into it, I'd rather hope to get an answer to the above "generic" question.
Other info:
bus-clock 24MHz
core-clock 240MHz, PEE mode
Fast peripheral clock 120MHz
Nanoedge clock 240MHz
Thanks in advance to any clarifying Info.
