Dealing with uA,PORTC5,when forced low draws less current than floating,why?

[diegocolombo]

Hi,please i nedd help

having to do with a battery i need to have my  KL15  uC  waiting in VLLS3 mode.

I can measure the current drawn by my board by a switched array of shunt resistors,@1 ohm on my DMM the tenth of uA are stable and readable.

PORTC_5 is used for wake up by a piezoelectric sensor,and it does work.

The odd thing is that when PTC5 is floating, i have 50uA consumption more than PTC5 kept low ,

Why?PTC5 is configured as GPIO by mux in PORTC_PCR5, and as input in GPIOC_PDDR.

Even hitting the piezo sensor,and so giving some transitions to PORTC5 has the same effect,and it happens even if the pin is not enabled for wake up(otherwise the measurement could not be done in this way).

any hint?

Many thanks

Diego

[kerryzhou]

Hi Diego,

      Thank you for your interesting in our kineits product.

      Could you tell me how did you configure your PTC5 as the VLLS3 wake up source? Did you configure the according LLWU module?

      Can you enter in the VLLS3 successfully? could you tell me your consumption.

      you can't use PTC5 wake up your vlls3,  I think maybe your configuration have some problems, so please check your configuration.

      If you use PTC5 as the VLLS3 wake up source, you should configurate the following points:

     1, set the ACKISO bit in PMC_REGSC

         if (PMC_REGSC &  PMC_REGSC_ACKISO_MASK)

            PMC_REGSC |= PMC_REGSC_ACKISO_MASK;

    2, Configure the PORTC_PCR5

      You can do it like this :

      PORTC_PCR5 = ( PORT_PCR_MUX(1) |

                   PORT_PCR_PE_MASK |

                   PORT_PCR_PFE_MASK |

                   PORT_PCR_PS_MASK

                     );

    3,  configure the LLWU module

     configure the dege detection for the wakup pin in LLWU_P9,

Actually, you can refer to the low power code in  our KL25 sample code, the link is :

http://www.freescale.com/files/32bit/software/KL25_SC.exe?WT_TYPE=Lab and Test Software&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe

After your configuration is correct, then test it again.

If you still have question, please let me know!

Best regards,

Jingjing

[diegocolombo]

Thanks JingJing Zhou,forgive me for being so late,in the last month it was vary difficult for me to be in contact with the forum

in order i configure PTC5 without selecting any pull resistor,to have high Z ,so that the piezo is not loaded

PORTC_PCR5 =  (  PORT_PCR_MUX(01));

the wake up is configured in this way

GPIOC_PDDR &= ~0x00000020; // set Port PTC5 as input once more,for safety

LLWU_PE3 &= ~LLWU_PE3_WUPE9_MASK;

LLWU_PE3 |=(WAKE_EVENT_ANY)<<LLWU_PE3_WUPE9_SHIFT;//WAKE_EVENT_ANY =3

the ACKISO bit was previously set as you are showing

so i think that the reason is the one that Earl Goodrich suggested.

In fact pulling slightly up or down the pin the problem disappears.

Thanks again

Diego

[egoodii]

All digital CMOS inputs are a totem-pole stack of a PMOS and an NMOS FET.  If the pin is allowed to 'float' a voltage between Vil and Vih can develop on the pin, which starts to bring BOTH transistors into the start of enhancement-mode.  As such both transistors will exhibit higher leakage than 'completely off' when driven to a 'valid' digital input voltage (<Vil or >Vih).  'Low Power' (and ideally ANY design) cannot allow CMOS input pins to 'float'.