DMA peripheral request - KL25

[Fan_xy]

Hello ,

As we know , kl25 has many dma peripheral requests and four DMA channels , and my question is when have a dma peripheral requests ,it will trigger which  DMA channle ?  where or which register config it  ?

Thank you!

[mjbcswitzerland · Accepted solution]

Hi

You define which peripheral trigger is used for each DMA channel in the DMAMUX.

Registers are

DMAMUX0_CHCFG0

DMAMUX0_CHCFG1

DMAMUX0_CHCFG2

DMAMUX0_CHCFG3

Regards

Mark

[Fan_xy]

hi Mark,

Thank you for help.

I find your said , use DMAUX0_CHCFGN -> SOURCE  define , while  where can find the peripheral trigger's slot number? for example , now i use UART _DMA trigger  DMA0 , the  slot number is ?  or the DMAMUX0_CHCFG0  is ?

Best Regards

Linda

[mjbcswitzerland]

Linda

These are the trigger defines that I use when working with the KL devices (not all triggers are available on particular devices)

Regards

Mark

#define DMAMUX_CHCFG_SOURCE_DISABLED	0	// 0x00
#define DMAMUX_CHCFG_SOURCE_UART0_RX	2	// 0x02 UART0 RX - DMAMUX_CHCFG_xx are available on DMA MUX 0 and on DMA MUX 1 (when available)
#define DMAMUX_CHCFG_SOURCE_UART0_TX	3	// 0x03 UART0 TX
#define DMAMUX_CHCFG_SOURCE_UART1_RX	4	// 0x04 UART1 RX
#define DMAMUX_CHCFG_SOURCE_UART1_TX	5	// 0x05 UART1 TX
#define DMAMUX_CHCFG_SOURCE_UART2_RX	6	// 0x06 UART2 RX
#define DMAMUX_CHCFG_SOURCE_UART2_TX	7	// 0x07 UART2 TX
#define DMAMUX_CHCFG_SOURCE_UART3_RX	8	// 0x08 UART3 RX
#define DMAMUX_CHCFG_SOURCE_UART3_TX	9	// 0x09 UART3 TX
#define DMAMUX_CHCFG_SOURCE_UART4_RX	10	// 0x0a UART4 RX
#define DMAMUX_CHCFG_SOURCE_UART4_TX	11	// 0x0b UART4 TX
#define DMAMUX_CHCFG_SOURCE_UART5_RX	12	// 0x0c UART5 RX
#define DMAMUX_CHCFG_SOURCE_UART5_TX	13	// 0x0d UART5 TX
#define DMAMUX_CHCFG_SOURCE_I2S0_RX	14	// 0x0e I2S0 RX
#define DMAMUX_CHCFG_SOURCE_I2S0_TX	15	// 0x0f I2S0 TX
#define DMAMUX_CHCFG_SOURCE_SPI0_RX	16	// 0x10 SPI0 RX
#define DMAMUX_CHCFG_SOURCE_SPI0_TX	17	// 0x11 SPI0 TX
#define DMAMUX_CHCFG_SOURCE_SPI1_RX	18	// 0x12 SPI1 RX
#define DMAMUX_CHCFG_SOURCE_SPI1_TX	19	// 0x13 SPI1 TX
#define DMAMUX_CHCFG_SOURCE_SPI2_RX	20	// 0x14 SPI2 RX
#define DMAMUX_CHCFG_SOURCE_SPI2_TX	21	// 0x15 SPI2 TX
#define DMAMUX0_CHCFG_SOURCE_I2C0	22	// 0x16 I2C0 - DMAMUX0_CHCFG_xx are only available on DMA MUX 0
#define DMAMUX0_CHCFG_SOURCE_I2C1_2	23	// 0x17 I2C1 (or I2C2)
#define DMAMUX_CHCFG_SOURCE_FTM0_C0	24	// 0x18 FTM0/TPM0 channel 0
#define DMAMUX_CHCFG_SOURCE_FTM0_C1	25	// 0x19 FTM0/TPM0 channel 1
#define DMAMUX_CHCFG_SOURCE_FTM0_C2	26	// 0x1a FTM0/TPM0 channel 2
#define DMAMUX_CHCFG_SOURCE_FTM0_C3	27	// 0x1b FTM0/TPM0 channel 3
#define DMAMUX_CHCFG_SOURCE_FTM0_C4	28	// 0x1c FTM0/TPM0 channel 4
#define DMAMUX_CHCFG_SOURCE_FTM0_C5	29	// 0x1d FTM0/TPM0 channel 5
#define DMAMUX_CHCFG_SOURCE_FTM0_C6	30	// 0x1e FTM0/TPM0 channel 6
#define DMAMUX_CHCFG_SOURCE_FTM0_C7	31	// 0x1f FTM0/TPM0 channel 7
#define DMAMUX0_CHCFG_SOURCE_FTM1_C0	32	// 0x20 FTM1/TPM1 channel 0
#define DMAMUX0_CHCFG_SOURCE_FTM1_C1	33	// 0x21 FTM1/TPM1 channel 1
#define DMAMUX0_CHCFG_SOURCE_FTM2_C0	34	// 0x22 FTM2/TPM2 channel 0
#define DMAMUX0_CHCFG_SOURCE_FTM2_C1	35	// 0x23 FTM2/TPM2 channel 1
#define DMAMUX_CHCFG_SOURCE_IEEE1588_T0	36	// 0x24 IEEE 1588 timer 0 (alternative)
#define DMAMUX0_CHCFG_SOURCE_FTM3_C1	36	// 0x24 FTM3 channel 1
#define DMAMUX_CHCFG_SOURCE_IEEE1588_T1	37	// 0x25 IEEE 1588 timer 1 (alternative)
#define DMAMUX0_CHCFG_SOURCE_FTM3_C2	37	// 0x25 FTM3 channel 2
#define DMAMUX_CHCFG_SOURCE_IEEE1588_T2	38	// 0x26 IEEE 1588 timer 2 (alternative)
#define DMAMUX0_CHCFG_SOURCE_FTM3_C3	38	// 0x26 FTM3 channel 3
#define DMAMUX_CHCFG_SOURCE_IEEE1588_T3	39	// 0x27 IEEE 1588 timer 3 (alternative)
#define DMAMUX_CHCFG_SOURCE_ADC0	40	// 0x28 ADC0
#define DMAMUX_CHCFG_SOURCE_ADC1	41	// 0x29 ADC1
#define DMAMUX0_CHCFG_SOURCE_CMP0	42	// 0x2a CMP0
#define DMAMUX0_CHCFG_SOURCE_CMP1	43	// 0x2b CMP1
#define DMAMUX0_CHCFG_SOURCE_CMP2	44	// 0x2c CMP2
#define DMAMUX_CHCFG_SOURCE_DAC0	45	// 0x2d DAC0
#define DMAMUX_CHCFG_SOURCE_DAC1	46	// 0x2e DAC1
#define DMAMUX0_CHCFG_SOURCE_CMT	47	// 0x2f CMT
#define DMAMUX0_CHCFG_SOURCE_PDB	48	// 0x30 PDB
#define DMAMUX0_CHCFG_SOURCE_PORTA	49	// 0x31 port A
#define DMAMUX0_CHCFG_SOURCE_PORTB	50	// 0x32 port B
#define DMAMUX0_CHCFG_SOURCE_PORTC	51	// 0x33 port C
#define DMAMUX0_CHCFG_SOURCE_PORTD	52	// 0x34 port D
#define DMAMUX0_CHCFG_SOURCE_PORTE	53	// 0x35 port E
#define DMAMUX0_CHCFG_SOURCE_TPM0_OVERFLOW	54	// 0x36 TPM0 overflow
#define DMAMUX0_CHCFG_SOURCE_TPM1_OVERFLOW	55	// 0x37 TPM1 overflow
#define DMAMUX0_CHCFG_SOURCE_TPM2_OVERFLOW	56	// 0x38 TPM2 overflow
#define DMAMUX0_CHCFG_SOURCE_TSI	57	// 0x39 TSI
#define DMAMUX_CHCFG_TRIG	0x40	// DMA channel trigger enable
#define DMAMUX_CHCFG_ENBL	0x80	// DMA channel enable

[Fan_xy]

Hi Mark,

Thank for your help.

And i have another question,  now I want use DMA transmit ADC result data.  I need collect two different signals use two  ADC channles  . And the in  kl25 , all of the adc channels  dma trigger are called ADC0,  my question is now I can't  use two DMA channals transmit two ADC data ,  do you have any good idea ?

Thank you !

Linda

[mjbcswitzerland]

Linda

The KL25 has one ADC controller. You can configure it for HW triggered mode so that it samples two channels automatically.

The results are available in ADC0_RA and ADC0_RB so it is possible to transfer these by configuring a DMA channel to copy two 16 bit words from ADC0_RA address on each trigger. The result is the two channels at the destination - if a buffer, the two channels will be stored Channel A, Channel B, Channel A, Channel B etc,

Or you can program two DMA channels with the same trigger and each one can copy either ADC0_RA or ADC0_RB to a buffer so that the channel data is not alternating.

Regards

Mark

[likong]

You can search "DMA request source" in RM, and you would find a table.