DMA Channel 4 Interrupt Problem

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DMA Channel 4 Interrupt Problem

Contributor I


I am using the MKE14Z256.

My application is using 6 DMA channels. 2 UARTs RX and TX use Channels 0-3.

Channel 4 is set up to move ADC Data when conversion completes. 

The DMA Channel 4 is set up to move 8 32 bit words to memory, and I can see that this completes.

The data is transferred and DMA-TCD4-CSR -> DONE bit gets set and DMA-TCD4-CSR -> INTMAJOR gets set.

Also DMA-INT->INT4 gets set and the Reference Manual says : "The outputs of this register are directly routed to the interrupt controller."

NVIC ISER indicates that the DMA0/4 transfer complete interrupt is enabled (Bit 0).

No interrupt occurs.

However, if I cause an interrupt on DMA Channel 0, DMA0_04_DriverIRQHandler(void) also checks the Channel 4 interrupt bit and executes the interrupt routine.

It appears that the DMA Channel 4 interrupt bit does not cause an interrupt. Am I missing something?


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2 Replies

Contributor I

To answer my own question, there appears to be a sneaky register in the SIM block called SIM_MISCTRL which has DMA_INT_SEL bits to select between shared channels. This is very confusing as there is an implication in several places that the interrupts are ORed together, but this register implies that DMA_INT_SEL[0] == 0 selects DMA Channel 0 and 1 selects DMA Channel 4. This documentation is very poor. There is no reference to this in the DMA part of the manual.

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Specialist V

Hi John

You have bought up a good point since there are a number of Kinetis parts that share eDMA channel interrupts:
- KE14Z/KE15Z - can select whether channels 0/4, 1/5, 2/6 or 3/7 are connected to the 4 available interrupt vectors (either/or)
- KL28 - are physically ORed (shared) with no further configuration option
- KL82 - can be optionally ORed (default is to having only 0,1,2 and 3 connected), as well as channels 4,5,6, and 7 can optionally be handled as extended interrupts via the INTMUX (then effectively 8 independent interrupt vectors)

There may be others but these show that there is no real pattern as to how the 'shared' interrupt are actually implemented.
If the lower order shared interrupts only are used it is simple and the same on all parts, but if the higher order shared ones are needed one must carefully study and maybe make some tests to be sure. Additional configuration and/or handling is needed and the fact that it may not always be possible to use all channel interrupts at the same time needs to be carefully considered when the channel allocation is defined (and possibly when the actual chip to be used is determined).



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