Gary
For 50MHz clock input (32 MHz is fastest crystal that can be used) the code can be taken from a K60 setup for the TWR board.
For 100MHz core/sytem clock, with 50MHz bus and 25MHz flash clocks the following (from the uTasker project) will do it:
#define CLOCK_MUL 32
#define MCG_C6_VDIV0_LOWEST depends on the K10 type used (either 24 or 16 - consult the particular data sheet)
#define CLOCK_DIV 16
#define SYSTEM_CLOCK_DIVIDE 1
#define BUS_CLOCK_DIVIDE 2
#define FLEX_CLOCK_DIVIDE 16 (not important if no Flex Bus)
#define FLASH_CLOCK_DIVIDE 4
MCG_C2 = (MCG_C2_RANGE_8M_32M | MCG_C2_LOCRE0); // select external clock source (with reset on clock loss)
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_1024); // switch to external input clock (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary since the FLL will not be used)
while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS);
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLEX_CLOCK_DIVIDE - 1) << 20) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024); // finally move from PBE to PEE mode - switch to PLL clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selectedSimulation showing the obtained speeds:
Regards
Mark
Gary
You can also generate code with PE.
The KDS code needs configuring, whereby you will also need to know the register content details since it needs raw settings configured. PE will allow you to not need to understand register settings but the generated code is pretty huge.
K10 120MHz
K10 100MHz
If using KDS you will also need to know this because you have to plug in the raw details, rather than being able to work with the actual divide and multiplications that you ultimately would like.
Therefore, for your K10 100MHz, a multiplication factor of x47 is 0x17, whereby for a K10 120MHz it is 0x1f.
#define MCG_C6_VDIV0_LOWEST 24 // when using K10 100MHz
or
#define MCG_C6_VDIV0_LOWEST 16 // when using K10 120MHz
allows the user to enter the value that is really required, eg, 47, and automates the actual register content used to match the chip.
The following article may help de-mystify the MCG and its operation http://www.utasker.com/kinetis/MCG.html
Regards
Mark
