static uint32_t test_source[4]={1,2,3,4};
static uint32_t test_dest[16]={0};
//DMA
//Enable DMA MUX
SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
// Disable DMA MUX channel first
DMAMUX0->CHCFG[0] = 0x00;
// Clear pending errors and/or the done bit
if (((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
DMA0->DMA[0].DSR_BCR |= DMA_DSR_BCR_DONE_MASK;
// Set Source Address
DMA0->DMA[0].SAR = (uint32_t )&test_source;
// Set destination address
DMA0->DMA[0].DAR = (uint32_t )&test_dest;
// Set BCR to know how many bytes to transfer
DMA0->DMA[0].DSR_BCR = DMA_DSR_BCR_BCR(64);
// Clear Source size and Destination size fields.
DMA0->DMA[0].DCR &= ~(DMA_DCR_SSIZE_MASK | DMA_DCR_DSIZE_MASK);
// Set DMA as follows:
// Source size is byte size
// Destination size is byte size
// D_REQ cleared automatically by hardware
// Destination address will be incremented after each transfer
// Cycle Steal mode
// External Requests are enabled
// Asynchronous DMA requests are enabled.
DMA0->DMA[0].DCR |= (DMA_DCR_SSIZE(0)
| DMA_DCR_DSIZE(0)
| DMA_DCR_D_REQ_MASK
| DMA_DCR_DINC_MASK
| DMA_DCR_SINC_MASK
| DMA_DCR_ERQ_MASK
//| DMA_DCR_CS_MASK
| DMA_DCR_ERQ_MASK
| DMA_DCR_EADREQ_MASK
| DMA_DCR_EINT_MASK
| DMA_DCR_SMOD(3)
);
// Enables the DMA channel and select the DMA Channel Source
//DMAMUX0->CHCFG[0] = 0x02; // Select UART0 as the Channel Source
DMAMUX0->CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK; // Enable the DMA MUX channel
NVIC_EnableIRQ(DMA0_IRQn);
DMA0->DMA[0].DCR |= DMA_DCR_START_MASK;
void DMA0_IRQHandler()
{
// Clear pending errors and/or the done bit
if (((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
| ((DMA0->DMA[0].DSR_BCR & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
DMA0->DMA[0].DSR_BCR |= DMA_DSR_BCR_DONE_MASK;
// Set BCR to know how many bytes to transfer
DMA0->DMA[0].DSR_BCR = DMA_DSR_BCR_BCR(64);
// Set Source Address (this is the UART0_D register
DMA0->DMA[0].SAR = (uint32_t )&test_source;
// Set destination address
DMA0->DMA[0].DAR = (uint32_t )&test_dest;
}
But After I run the code instead of getting 1,2,3,4,1,2,3,4... in test_dest I will get