In my opinion, when it comes to ultra low power, it is about code size and cycle counting. The KL05-SC samples are somewhat disappointing in this respect. For example they do not use the port PCOR and PSOR functions properly and they do not show how to make use of the BME module. Did i miss something? Does the processor expert do it better, or one of the development environments? I am looking for samples or proposals on using the BME in a systematic fashion. At least there should be a set of macros like those mentioned in the reference manual.
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In the meantime i found the LQRUG_bme_ex1 sample, so i have to answer myself..
In that sample we have macro definitions for BME as inlinine C functions. Once i got those functions really inlined by the compiler, results were as expected: While the standard C implementations needed 13 or 14 systicks, BME achieved the same in 10 or 11 systicks. In general BME was faster by 4 systicks per operation, or 40 %.
With an optimizing compiler the things get confusing. For example once the processor has an address register for GPIOA_PDDR it may reuse it inside the benchmark for the logical operation on GPIOA_PDOR (which is nearby), while BME needs a completely new destination address.
In the meantime i found the LQRUG_bme_ex1 sample, so i have to answer myself..
In that sample we have macro definitions for BME as inlinine C functions. Once i got those functions really inlined by the compiler, results were as expected: While the standard C implementations needed 13 or 14 systicks, BME achieved the same in 10 or 11 systicks. In general BME was faster by 4 systicks per operation, or 40 %.
With an optimizing compiler the things get confusing. For example once the processor has an address register for GPIOA_PDDR it may reuse it inside the benchmark for the logical operation on GPIOA_PDOR (which is nearby), while BME needs a completely new destination address.