ADC clock below 2.0MHz limit

[asfarley]

I'm getting  a compiler warning after adding 2 ADCs to my project using Processor Expert: ADC clock is below the 2.0MHz limit. 

I followed the default PE configuration and PE doesn't show any errors. The ADCs are mostly working correctly; I'm getting good readings if I measure against GND or VSS for both ADC channels with the exception that one channel seems to be loading the source more than the other. The slowest clock rate is selected (19.2 us).

I have Clock cfg 0 set to "Auto select" for both ADCs. It seems like PE is auto-selecting a clock configuration that isn't correct for the ADCs. Any idea why PE auto-selects a clock that the compiler complains about? 

*Edit: The channel loading issues were simply caused by external hardware on the FRDM board).

[lucapeterlini]

I am getting the same warning.

Have solved this problem? Did you have any trouble in ADC conversion or besides the warning message every thing is working properly?

[vicentegomez]

I'm glad that you solve your issue.

Have a good day.

[asfarley]

I haven't solved the main issue - I just figured out why one ADC channel seemed to have a load on it already. The main issue is, why am I getting the 2.0MHz warning using default configuration?

[vicentegomez]

Can you please share your code?

Thanks

[lucapeterlini]

It's a Processor Expert problem/warning. Why should code matter? I haven't any code yet and the warning is showing all the same. You also thought that he have solved his problem when he obviously didn't said that. Are you reading what people write or just answer anything to mark as contribution?

[asfarley]

Here's a link to my ProcessorExpert.pe file:

https://dl.dropboxusercontent.com/u/59343634/ProcessorExpert.pe 

My ADC clock configuration is below. Please let me know if you need any other code. 

Basically, I'm just wondering why the default ADC clock values result in compiler warnings.