SGTL5000 clock inputs

[leoramikam]

Hi.  If I want to use the internal PLL driven from the external SYS_MCLK input, what do I do with the i2s clock input pins?  Do they need to be grounded?

[xiangjun_rong]

Hi, Leor,

I am not very familiar with the codec SGTL5000, I have just browsed the data sheet of SGTL5000, I think you should connect the SYS_MCLK to a clock even if you set up the SGTL5000 in slave mode(the I2S_LRCLK and I2S_SCLK are all driven by external processor),

Pls refer to the remarks in Data sheet:

"

The I2S_LRCLK and I2S_SCLK can be programmed as master (driven to an external target) or slave (driven from an external source). When the clocks are in slave mode, they must be synchronous to SYS_MCLK. For this reason the SGTL5000 can only operate in synchronous mode (see Clocking) while in I2S slave mode

"

In other words, sys_mclk should be eaual to 256*Fs, or 384*Fs or 512*Fs. pls refer to Table 8. Synchronous MCLK Rates and Sampling Frequencies even if in slave mode.

BR

XiangJun Rong