Relationship between jtagclk and programming speed for MC56F8323

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Relationship between jtagclk and programming speed for MC56F8323

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jancoufal
Contributor I

Hello

We use MC56F8323 and we recently encountered a problem, where the flash memory changes itself on the higher temperatures ( >95°C).

Thanks to this forum we found out, that problem is caused by improper setting of FMCLKD register during initialization of our bootloader, which lead to the wrong programming speed (2Mhz)

 

For some reason, we cannot change the bootloader code, so we adjusted manufacturing process to not use our bootloader (with improper settings), but JTAG connector and FlashProgrammer tool (v1.2)

 

However, there is a question about jtagclk and its relation to the programming speed.

The 56800E Flash Programmer User Guide says about -jtagclk this:

This option tells the CCS server the frequency (kHz) to run the JTAG interface. The default value is 800kHz. Faster clock speeds allow for faster programming, but if the clock is set too fast, the DSC chip may not be able to process incoming data quickly enough, eventually leading to a programming failure.


And the 56F8300 Peripheral User Manual requires the programming speed to be between 150-200kHz:

Setting FMCLKD to a value so FCLK <150kHz can destroy the Flash due to overstress. Setting FMCLKD to a value so FCLK >200kHz can result in incomplete programming or erasure of the memory array cells.

 

 

Our questions are:

Is -jtagclk speed related to the programming speed and FMCLKD setting? And if so, then how? (1:1 ratio?)

How should we set this option to ensure that programming speed will be correct?

 

 

Thanks

Jan Coufal

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xiangjun_rong
NXP TechSupport
NXP TechSupport

The JTAG port clock and Flash clock are totally different clock source. For the Jtag port clock, as you know, the JTAG signals consist of Reset, TMS, TDI, TDO, TCK, the TCK signal is the JTAG clock, the so-called 8KHz JTAG clock is the TCK clock, the TCK is an input pin for DSC, external source should drive the pin.

The flash operation also needs clock, in general, the divider of bus clock can be the Flash clock FCLK,  in order to operate properly, the FCLK should range from 150KHz to 200KHz. I suppose you use Codewarrior for DSP56800/E ver8.3 tools, pls refer to the directory: C:\Program Files (x86)\Freescale\CodeWarrior for DSC56800E v8.3\M56800E Support\initialization, for example, open the 568346_flash.cfg, there is the line in the file:

# set_hfmclkd 0x14  # if no ALS
set_hfmclkd   0x0A 

# if ALS (best flash freq spec)

when CW tools download code, the PLL is not used, the external clock source is 8MHz, bus clock is 4MHz, the driving flash clock is 2MHz, DIV=0A, which means that the FCLK is 2MHz/10=200KHz.

when downloading code to flash, the CW has to erase the flash, program the flash, the two operation is time-consuming, so increasing JTAG clock TCK frequency has limited effect to fast downloading. Because the erasing/programing flash determine the downloading time.

BTW, FMCLKD register can only be written once after Reset.

Hope it can help you.

BR

Xiangjun Rong

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xiangjun_rong
NXP TechSupport
NXP TechSupport

The JTAG port clock and Flash clock are totally different clock source. For the Jtag port clock, as you know, the JTAG signals consist of Reset, TMS, TDI, TDO, TCK, the TCK signal is the JTAG clock, the so-called 8KHz JTAG clock is the TCK clock, the TCK is an input pin for DSC, external source should drive the pin.

The flash operation also needs clock, in general, the divider of bus clock can be the Flash clock FCLK,  in order to operate properly, the FCLK should range from 150KHz to 200KHz. I suppose you use Codewarrior for DSP56800/E ver8.3 tools, pls refer to the directory: C:\Program Files (x86)\Freescale\CodeWarrior for DSC56800E v8.3\M56800E Support\initialization, for example, open the 568346_flash.cfg, there is the line in the file:

# set_hfmclkd 0x14  # if no ALS
set_hfmclkd   0x0A 

# if ALS (best flash freq spec)

when CW tools download code, the PLL is not used, the external clock source is 8MHz, bus clock is 4MHz, the driving flash clock is 2MHz, DIV=0A, which means that the FCLK is 2MHz/10=200KHz.

when downloading code to flash, the CW has to erase the flash, program the flash, the two operation is time-consuming, so increasing JTAG clock TCK frequency has limited effect to fast downloading. Because the erasing/programing flash determine the downloading time.

BTW, FMCLKD register can only be written once after Reset.

Hope it can help you.

BR

Xiangjun Rong

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jancoufal
Contributor I

Thank you, that is exactly what I am looking for.

Cheers.

Jan Coufal

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