I suppose that the Receiver idle can trigger interrupt vector 52. You can enable the Receiver idle interrupt by setting the RIIE bit QSCIx_CTRL2, in the ISR of vector 52, you can check the RIDLE bit in QSCIx_STAT, if it is set you can see that Receiver idle happens.
As a test, in the ISR of vector 52, you can check the RIDLE bit, if it is set, toggle a GPIO. You can check the GPIO pin waveform to know if the receiver idle happens or not.
Thank you for your answer.
RIDLE bit is set after a message received, but it does not trigger vectors from 51 to 54.
It seems an individual vector, but where?
Pls refer to the vector table, there are 2 interrupt vectors for the SCI0 receiver, so I suspect the idle interrupt of receiver is included in vector 51 or 52, especially 52.
You can have a try by generating the receiver interrupt and set a break point in two ISR and check which is entered.
I have checked 51 and 52 many times, no one can be entered after Ridle flg set.
From Table 35-39 I attached days ago, I think there is an independent vector for Ridle.
thanks a lot
I got feedback from design team, the SCI0 Receiver idle interrupt is not routed to interrupt table vector by mistake, so SCI0 receiver idle interrupt can not be triggered. We will document the issue in the errata.
Thank you for pointing the error.
I tested many times accordding to your suggestion.
I enabled the RFIE & RIIE, and the DMA transported whole message correctly as below:
when a message ended, I checked the relative registors as bellow: RIDLE Flag is set.
but no any interrupt requist pending up: