MC56F84789 Problem with DMA SCI - receiver idle interrupt

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MC56F84789 Problem with DMA SCI - receiver idle interrupt

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Contributor I

Hello,

I have problem with DMA SCI on receiver idle interrupt.

I wrote the codes of SCI receiver by DMA  and it works well.

But when I try to add receiver idle interrupt, I can not find where the receiver idle interrupt vecteor is.

I have to search the whole <MC56F847xx Reference Manual> but no more information except bellows:

 

1.pngAt the middle-left of the Figure 35-28,  there is a receiver idle interrupt Request.

But it does not exist in Table 3-10. Interrupt Vector Table:

2.png

And I can not find any relative information in CodeWarrior PE.

Please help me, thanks.

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9 Replies

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NXP TechSupport
NXP TechSupport

Hi, WangJun,

I suppose that the Receiver idle can trigger interrupt vector 52. You can enable the Receiver idle interrupt by setting the RIIE bit QSCIx_CTRL2, in the ISR of vector 52, you can check the RIDLE bit in QSCIx_STAT, if it is set you can see that Receiver idle happens.

As a test, in the ISR of vector 52, you can check the RIDLE bit, if it is set, toggle a GPIO. You can check the GPIO pin waveform to know if the receiver idle happens or not.

BR

XiangJun Rong

pastedImage_1.png

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Contributor I

Dear Mr.rong,

Thank you for your answer.

RIDLE bit is set after a message received, but it does not trigger vectors from 51 to 54.

4.png

It seems an individual vector, but where?

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NXP TechSupport
NXP TechSupport

Hi, Jun,

Pls refer to the vector table, there are 2 interrupt vectors for the SCI0 receiver, so I suspect the idle interrupt of receiver is included in vector 51 or 52, especially 52.

You can have a try by generating the receiver interrupt and set a break point in two ISR and check which is entered.

BR

XiangJun Rong

pastedImage_1.png

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233 Views
Contributor I

Mr. rong,

I have checked 51 and 52 many times, no one can be entered after Ridle flg set.

From Table 35-39 I attached days ago, I think there is an independent vector for Ridle.

thanks a lot

 Jun Wang

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NXP TechSupport
NXP TechSupport

Hi,WangJun,

How about checking the INTC_IRQP3 reg to know if the SCI receiver idle interrupt happens or not?

BR

Xiangjun Rong

pastedImage_1.png

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233 Views
Contributor I

Hi, Mr.rong

any new information?

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NXP TechSupport
NXP TechSupport

Hi, WangJun,

I got feedback from design team, the SCI0 Receiver idle interrupt is not routed to interrupt table vector by mistake, so SCI0 receiver idle interrupt can not be triggered. We will document the issue in the errata.

Thank you for pointing the error.

BR

Xiangjun Rong

 

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Contributor I

Hi, Mr.rong

I tested many times accordding to your suggestion.

Image 4.jpg

I enabled the RFIE & RIIE, and the DMA transported whole message correctly as below:

Image 3.jpg

when a message ended, I checked the relative registors as bellow: RIDLE Flag is set.

Image 1.jpg

but no any interrupt requist  pending up:

Image 2.jpg

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233 Views
Contributor I

Image 5.jpg

No any interrupt request.

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