i have a question about the MC56F8255 flash-clockdivider (register HFM_CLKD.Div[5..0]):
says i should avoid:
(1/Fclk - 4/Fbus) < 5us
In the CodeWarrior folder i can find the flash.cfg file for the MC56f8255 (5625x_flash.cfg) here:
In this this .cfg-file i can see the following entry:
set_hfmclkd 0x27 (0x27 = 39dez)
After Reset, MSTR_OSC = 8MHz (internal OSC aktiv), so Fclk is:
Fclk = MSTR_OSC / (hfmclkd + 1)
Fclk = 8MHz / (39 + 1) = 8MHz / 40 = 200kHz
After Reset Fbus is 8MHz (internal OSC aktiv). When i'm testing the above standing rule i get the following result:
(1/Fclk - 4/Fbus) should be >= 5us
(1/200kHz - 4/8MHz) = 4,5us
So the set_hfmclkd value in the init-file from the CodeWarrior-installation folder should be an illegal value. Is this correct?
The second question: Have i proberly understood that Fclk is always MSTR_OSC and not the sys_clk / 2? For Example the PLL is aktiv and the sys_clk = 60MHz, then the Fclk for flash-programming is MSTR_OSC = 8MHz and NOT 30MHz? So this were different from the flash-programming for the MC56F83xx. The MC56F83xx use for flash-programming sys_clk / 2 (30MHz in the example above).
Many thanks for your help!
Hi XiangJun Rong,
you'r answer can't be correct! You wrote "16.6nS-16.6nS/4=12.45nS, which is obviously less than 5us", but in the datasheet stands you should AVOID results <5us. And 12,45ns is much less than 5us but have to be >=5us. I think the rule in the user Manual at page 612/613:
(1/Fclk - 1/(4*Fbus)) must be >= 5us
is correct! (Fclk instead of Fbus)
Then the Divider in the .cfg-File 39 (0x27) is not correct and must be 40 (0x28) or greater to satisfy this rule.
Hello XiangJun Rong,
many thanks for your help. I thought it was a spelling mistake, because in the Reference Manual http://www.nxp.com/assets/documents/data/en/reference-manuals/MC56F825XRM.pdf at the end of the page 612 (Kap. 20.3.5) under "Caution" stands the rule: (1 / Fclk) - (1 / Fbus / 4) < 5us.
As the following screenshot, the formula is ((1 / FBUS[MHz]) - (1 / FBUS[MHz] / 4)) < 5 μs, it is the Fbus clock instead of flash clock. The Fbus clock is the system bus clock, generally, the Fbus system bus clock is 60MHz, the cycle time is 16.6nS, of course, the formula 16.6nS-16.6nS/4=12.45nS, which is obviously less than 5us.
As the next note said that "With an FBUS value below 1 MHz, erasing and writing flash are not possible, but reading
flash is still supported.", If the systrem bus clock is too low, the flash writting stress will be high, the scenario should be avoided.
Hope it can help you