DMA support on I2C(MC56F82748)

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DMA support on I2C(MC56F82748)

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EngHuiPeng
NXP Employee
NXP Employee

When TCF bit is asserted, a DMA request is initiated. Does this mean the DMA CH0 will be starting to transfer data and make the SDA line as GPIO, is this  automatically done without asserting the start for DMA CH0? Then inside the ISR handler, after setting the DMA CH2 source and destination, DMA_DCR1 start bit is the one asserted. This means DMA CH1 will be started, making the SDA pin as peripheral mode. Now, when is the DMA CH2 data transfer started? Can you see any assertion of DMA_DCR2 start bit. Is the transfer automatically done after DMA_CH1 finished transferring data? Will PE configuration linking DMA CH1 to DMA CH2.

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EngHuiPeng
NXP Employee
NXP Employee

XiangJun, They should be using one Channel but because of the sample code we gave them is 2 channel. We have a better understanding now. Thanks. Regards, Audrey

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, HuiPeng,

Regarding your question, I do not understand why you use TWO DMA channels(DMA_CH0 and DMA_CH1) to transfer data. In general, if you do not want to implement the DMA channel linking function, just want to transfer data from IIC data register to memory or transfer data from memory to IIC data register, I think it is okay to use just ONE DMA channel.

All four DMA modules support IIC data transfer, assume that you use DMA_CH0 to transfer IIC data register to memory, this is the IIC and DMA_CH0 modules configuration.

1)configure the IIC module and set the DMAEN bit in I2C_C1 register.

2)configure DMA_CH0, set the CFSM0 bit to reset the DMA state machine, set the DMAC0 as 4.

3)set the DMA source register DMA_SAR0=(long)0xE0E4<<1; //Byte address //address of I2C_D is 0xE0E4 for MC56F827xx

4)define a static array to save data for example unsigned int array[100], set the destination register: DMA_DAR0=(long)&array[0]<<1; //byte address

5)initialize the DMA_DCR0 based on your application. in the example, it is IIC master reading from IIC data reg to memory, DMA_DCR0 can be 0xE02C0000

6)it is okay.

I do not think the DMA transfer is related to SDA line as GPIO, the DMA is only used to transfer data, the SDA line functions as open drain SDA function of IIC module in the DMA transfer procedure. If you use link function of DMA to set the SDA pin as GPIO by writing the F3 bit in SIM_GPSFL by another linked DMA channel on purpose, it is another story.

Hope it can help you.

BR

Xiangjun Rong

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