rebooting the 5485 with software?

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rebooting the 5485 with software?

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Dietrich
Contributor II
This message contains an entire topic ported from the WildRice - Coldfire forum.  Freescale has received the approval from the WildRice administrator on seeding the Freescale forum with messages.  The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value as you search for answers to your questions.  Freescale assumes no responsibility whatsoever with respect to Posted Material.  For additional information, please see the Terms of Use - Message Boards and Community Forums.  Thank You and Enjoy the Forum!
 

Mar 28, 2006, 12:48 PM
Post #1 of 8 (6 views)
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 [ColdFire] rebooting the 5485 with software?  Can't Post 
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Does, anybody know a simple way to reset a 5485 by using software? We
have a requirement here where we need to invoke a processor reset by
software.
Thanks,
--------------------------------------------------------------------
Mar 28, 2006, 12:59 PM
Post #2 of 8 (6 views)
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 RE: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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If your product has a watchdog with a reasonably short timeout period, you
could simply disable interrupts and enter an endless loop.
-----Original Message-----
From: On
Behalf Of Chaloupka, Karel
Sent: Tuesday, March 28, 2006 12:49 PM
To: 
Subject: [ColdFire] rebooting the 5485 with software?

Does, anybody know a simple way to reset a 5485 by using software? We
have a requirement here where we need to invoke a processor reset by
software.
Thanks,
--------------------------------------------------------------------
Mar 28, 2006, 1:01 PM
Post #3 of 8 (6 views)
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 Re: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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I don't know if you're using Linux, but if you are,
you can do a system("reboot"); call from a c program
as a very high level solution.
--- "Chaloupka, Karel" <>
wrote:
> Does, anybody know a simple way to reset a 5485 by
> using software? We
> have a requirement here where we need to invoke a
> processor reset by
> software.
>
> Thanks,
>
>
--------------------------------------------------------------------
Mar 28, 2006, 1:15 PM
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 RE: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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I know in the 5282 there's a bit in the Reset Status Register (RSR) called
SOFTRST. Setting this bit will force a reset.
I reviewed the data sheet for the 5485 and it doesn't appear to have the
same bit. If you have the watchdog enabled, you could disable interrupts
and run an infinite loop until the watchdog resets.
Mark

-----Original Message-----
From: 
Behalf Of Chaloupka, Karel
Sent: March 28, 2006 3:49 PM
To:
Subject: [ColdFire] rebooting the 5485 with software?
Does, anybody know a simple way to reset a 5485 by using software? We
have a requirement here where we need to invoke a processor reset by
software.
Thanks,
--------------------------------------------------------------------
Mar 28, 2006, 1:17 PM
Post #5 of 8 (6 views)
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 Re: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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You can use the internal watchdog in GPT0. Set it to some 10ms, then
just wait and see the fireworks... :smileyhappy:
Best regards
Luca Burelli
"I have seen things you people would not believe. Attack ships on fire off
the shoulder of Orion. C-beams glittering in the dark near the Tannhauser
Gate. But... all those moments will be lost in time, like tears in rain."
(Roy Batty, from Blade Runner, 1982)
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On Tue, 28 Mar 2006, Chaloupka, Karel wrote:
> Does, anybody know a simple way to reset a 5485 by using software? We
> have a requirement here where we need to invoke a processor reset by
> software.
>
> Thanks,
>
> --------------------------------------------------------------------
Mar 28, 2006, 1:17 PM
Post #6 of 8 (6 views)
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 Re: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
--------------------------------------------------------------------------------
 
You can use the internal watchdog in GPT0. Set it to some 10ms, then
just wait and see the fireworks... :smileyhappy:
Best regards
Luca Burelli
"I have seen things you people would not believe. Attack ships on fire off
the shoulder of Orion. C-beams glittering in the dark near the Tannhauser
Gate. But... all those moments will be lost in time, like tears in rain."
(Roy Batty, from Blade Runner, 1982)
_
ASCII ribbon campaign ( )
- against HTML email X
& vCards / \
On Tue, 28 Mar 2006, Chaloupka, Karel wrote:
> Does, anybody know a simple way to reset a 5485 by using software? We
> have a requirement here where we need to invoke a processor reset by
> software.
>
> Thanks,
>
> --------------------------------------------------------------------
Mar 28, 2006, 1:43 PM
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 Re: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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This is the routine we use that does what others have suggested - enable
the Watchdog timer and wait for it to expire. The isrMasked() and
isrMask() routines are specific to our RTOS, but it shouldn't be too
hard for you to get this to compile. We use it on MCF547X/8x boards.
/***********************************************************************/
/* bspReset: Reset the board and CPU */
/* */
/***********************************************************************/
void bspReset(void)
{
if (!isrMasked())
fclose(stdin);
isrMask();
MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(1) | MCF_GPT_GCIR_CNT(2);
MCF_GPT_GMS0 = MCF_GPT_GMS_CE | MCF_GPT_GMS_WDEN |
MCF_GPT_GMS_TMS_GPIO;
while (MCF_GPT_GMS0) ;
}
Tim
----- Original Message -----
From: "Chaloupka, Karel" <>
To: stout@blunkmicro.com
Sent: Tuesday, March 28, 2006 12:48 PM
Subject: [ColdFire] rebooting the 5485 with software?

Does, anybody know a simple way to reset a 5485 by using software? We
have a requirement here where we need to invoke a processor reset by
software.
Thanks,
--------------------------------------------------------------------
Mar 28, 2006, 2:27 PM
Post #8 of 8 (6 views)
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 RE: [ColdFire] rebooting the 5485 with software? [In reply to]  Can't Post 
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We used a GPIO line and (wire anded it in with our reset along with the
BDM reset) pretty simple we use it to reset our box after a software
update. All the devices are tied together to open collector. Works
great.
 
Gregg GRANVILLE
Hardware Engineering Manager
-------------------------------------
Tel 1 603.622.0212 / Fax 1 603.623.5623
ggranville@metronics.com/ www.metronics.com
--------------------------------------------------------
METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US
-----Original Message-----
From: On Behalf Of Doug Leany
Sent: Tuesday, March 28, 2006 3:59 PM
To: Granville Gregg
Subject: RE: [ColdFire] rebooting the 5485 with software?
If your product has a watchdog with a reasonably short timeout period,
you
could simply disable interrupts and enter an endless loop.
-----Original Message-----
From: On Behalf Of Chaloupka, Karel
Sent: Tuesday, March 28, 2006 12:49 PM
To: DLEANY@Opto22.com
Subject: [ColdFire] rebooting the 5485 with software?

Does, anybody know a simple way to reset a 5485 by using software? We
have a requirement here where we need to invoke a processor reset by
software.
Thanks,
 
 
 

Message Edited by Dietrich on 04-03-2006 11:11 AM

Message Edited by Dietrich on 04-04-2006 01:25 PM

Message Edited by Dietrich on 04-04-2006 01:35 PM

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7 Replies

808 Views
kwong
Contributor I
I've tried the above solution, but it intermittently fails.  We attached a scope to the RSTO line coming out of the our 5474 processor and noticed that the reset line is only held low for about 40ns.

This is too short for resetting the flash chips on our board.  Is there any way of lengthening how long the reset output line is held low for when the watchdog is triggered?

Ken.
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schiller
Contributor III

Hi Ken,

 

I'm facing the same problem. Did you find a solution ?

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kevin_curtis
Contributor I

We are running 2.6.29 kernel (CFLINUX_20100901) on a MCF5474-based design. When we execute a reboot command from Linux, this eventually calls the machine_restart() function that calls mach_reset() (=coldfire_reboot()), which disables interrupts, enables a short watchdog timeout and halts at a forever loop if the watchdog doesn't reset first. What we have found is that the reset by the watchdog intermittently fails, maybe 1 in 10.

We have a BDM with GDB attached and a logic analyser on the flex bus. When the CPU fails to start, it has hung at address zero; the chip select registers appear to have been correctly reset (only CS0 enabled, with max wait states); if we try and display the beginning of the NOR Flash memory using GDB where the reset vector resides we read back all zeroes, yet the logic analyzer shows /CSO being asserted and the NOR flash driving the reset vector and initial stack pointer setting onto the flex bus.

Any ideas what the problem may be?

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TomE
Specialist II

kevin_curtis wrote:

When the CPU fails to start, it has hung at address zero; the chip select registers appear to have been correctly reset (only CS0 enabled, with max wait states);

Any ideas what the problem may be?


It might be a similar one to this:

 

https://community.freescale.com/message/100188#100188

 

These chips all have "force a few address or data pins to specific levels during reset" to set a bunch of startup options. With the MCF5301X it seems there is at least one pin that must be driven on reset, but none of the documentation lists it. It is unlikely the same would be happening with your chip, but it is something to check.

 

More likely is that you're not driving all of AD[12:8] properly on reset, or that some other chip on the bus is intermittently jamming them during reset.

 

Another suggestion on reset, make sure you've disabled the cache in case the chip is being reset during a cache flush operation.

 

Tom

 

 

 

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kevin_curtis
Contributor I

Hi Tom,

    thanks for your two answers to my question, it is much appreciated.  We will certainly check out all of your suggestions and post our finding back here.

 

Regards

 

Kevin

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kevin_curtis
Contributor I

It was brought to our attention that the M5474LITE development board is configured to run with a 66MHz CLKIN and 1:2 bus ratio which results in 66MHz PCI/FlexBus, 133MHz SDRAM and 266MHz Core frequencies. Our own MCF5474-based design was configured to run with 33MHz CLKIN and 1:4 bus ratio which results in 33MHz PCI/FlexBus, 133MHz SDRAM and 266MHz Core frequencies.

 

After modifying our design to run 66MHz CLKIN with a 1:2 bus ratio, we retested with an auto reset on U-Boot (bootdelay 10, bootcmd reset) and successfully restarted more than 27000 times. Previously it hung roughly 1 in 10 restart attempts and I had never seen more than 28 restarts without it hanging.

 

Errata SEFC077 documents a 1:4 bus ratio fault that can result in a FlexBus hang, but does not mention anything to do with a Watchdog reset hang. The workaround mentioned in SEFC077 did not affect the reliability of the Watchdog reset.

 

Thanks TomE for your suggestions, but we didn't have any success with selectively shutting down components prior to initiating the watchdog reset with 33MHz CLKIN.

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TomE
Specialist II

Check the Errata. There's nothing obvious in there, but make sure you don't have an old chip with SECF060.


Are you generating a "very short reset" like one of the other posters had that might not be resetting your FLASH chips properly? Is it possible to switch the CPU to running on a slower clock before generating the watchdog? You might be able to get a longer reset that way.

 

it is always worth deliberately shutting everything down prior to a reset if you can, like resetting all controllers, stoppng DMA and Interrupts, disable the DRAM, reset the GPIO pins, slow down the CPU and so on. If you do that and the problem goes away you can find out which change did it and zero in on the original problem. Do you have pullups/downs on any sensitive pins that tri-state durng reset?

 

Do the FlexBus and DDRAM controller share any data pins, like the Series 2 and 3 ones do (it looks like they don't)? Do you have any other peripherals on your data bus? A lot of these chips have problems when they reset during a DRAM cycle, as the DRAM can then lock up and jam the busses. Likewise some peripherals if active when their bus cycle is aborted during reset. Refer to the descriptions here:

 

https://community.freescale.com/message/69745#69745

 

Tom

 

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