no PST_CLK output in BDM mode

[changliu1]

On my board, a MCF54415 is used in BDM mode. I am sure that JTAG_EN is low, RESET is high, Power is in the range of recommand value, clock is 50MHz, FB_CLK output in 62.5MHz. But no PST_CLK output and MCF54415 can't run in BDM mode with P&E MULTILINK. What factor can influence PST_CLK? Some error in BOOTMODE or BOOT Config can lead to that?

[changliu1]

The problem is solved.  FlexBUS of MCF54415 is connected to a lattice CPLD and programn signal of CPLD is connected to resetout of MCF54415. When board power up, MCF54415 output a 20ms low on resetout signal, then all pins of CPLD is tied to ground. But at the same time, FB_AD9 output high low. So the actual voltage of FB_AD9 is only 1.2V. When resetout is high again, FB_AD9 and pins of CPLD recover to tri-state. But no PST_CLK output, and MCF54415 can not enter in BDM mode. After I disconnect the resetout of MCF54415 and programn pin of CPLD, everything is OK.