Ok, so far the feedback I have gotten from freescale support on this is sample code with time delays where I had them in my code. Not so helpful (except for Tom, his advice has been helpful).
I have discovered something that can be done to avoid using time delays.
Check for the following items in the following order:
1) Peripheral address to be equal to what it is loaded to. while(MCF_I2C0_I2DR != (address))
2) Transfer complete flag to be set. while(!(MCF_I2C0_I2SR & MCF_I2C_I2SR_ICF))
See snippet below for how I integrated it into my code. So far this has worked repeatedly and reliably. For anyone considering this method, please keep in mind this is something I came up with under an aggressive schedule and hasn't been fully regression tested. So.... use at your own risk.
It would be nice if someone from Freescale could either validate this solution or come up with something better.
// set transmit mode: bit 4 = 1;
MCF_I2C0_I2CR |= MCF_I2C_I2CR_MTX;
// send ACK after receive
MCF_I2C0_I2CR &= ~MCF_I2C_I2CR_TXAK;
// set MSTA to 1 to generate START condition
MCF_I2C0_I2CR |= MCF_I2C_I2CR_MSTA;
// set slave address
MCF_I2C0_I2DR = address;
//* wait for bus busy *//
loop_count2 = 0;
while(!(MCF_I2C0_I2SR & MCF_I2C_I2SR_IBB)) //if bus is idle, wait until busy
{
loop_count2++;
if(loop_count2 > LOOP_TIMEOUT)
{
break;
}
}
loop_count2 = 0;
while(MCF_I2C0_I2DR != address)
{
loop_count2++;
if(loop_count2 > LOOP_TIMEOUT)
{
break;
}
}
loop_count2 = 0;
while(!(MCF_I2C0_I2SR & MCF_I2C_I2SR_ICF))
{
loop_count2++;
if(loop_count2 > LOOP_TIMEOUT)
{
break;
}
}
// wait until transfer finish
//---------------------------
_lwsem_wait( &i2c_ready_semaphore );
// _time_delay(5);
MCF_I2C0_I2DR = *(unsigned char *)(data + i); //load data onto i2c bus.