eDMA / SDRAM access causes core lockup on MCF54453.

[Thad]

In our application, the eDMA is reading 18 words of data from a memory-mapped FPGA and placing them into a 2.25Kb SDRAM (DDR2) area.  After the transfer is complete, the core (firmware) reads data from this shared SDRAM region. After the core is done reading the data, the eDMA runs again to get the next 18 words of data and puts them in a different location in the 2.25Kb section of SDRAM. 

What we are seeing is after the application runs for a few seconds, the CPU appears to lock up.  The Green Hills debugger can't halt the CPU.  A reset or power cycle is required to bring the CPU back.  If I disable the reads by the core to the shared SDRAM, the problem does not occur.  If I have the core read data from SDRAM outside of the 8K block, the problem does not occur.  The problem only happens at low temps (5 C - which is not very low) and high temps.  It seems to work at room temperature.  According to your documentation the crossbar switch should be handling the accesses by the eDMA and the core.  What is going on that could cause the core to completely go out to lunch?

This is a show stopper since we are begining our temperature testing and it can't pass at 5 C.

[Thad · Accepted solution]

jehoffma,

Thanks for the post; that put us on the right track.  We didn't change the memory bus speed but instead tweaked the burst read to read/precharge delay in the SDCFG2 register from 5 up to 6.  No lock-up so far, though a longer run in our test chamber will be needed before I can say for certain that we've fixed it.  I'll follow-up when I have more info.

Thanks again,

Thad

[Thad]

Just a follow-up to confirm that the SDCFG2 tweak seems to have done the trick.  Its been running flawlessly in our test chamber for a while now.

Thad

[jehoffma]

Hi Thad,

may I ask what were your thoughts/presumptions that lead to the SDCFG2 change?

Jens

[jehoffma]

Hi Thad,

we had similar problems with our board based on a MCF54451. The SDRAM was clocked at 100MHz and beginning at 20 centigrade the board locked up. As workaround we lowered the SDCLK down to 80MHz and now it is running for a few weeks, but the lockup still occurs at 40 centigrade.