When is CCR.V bit set?

[tupdegrove]

General question not related to specific device.  I understand it is an arithmetic overflow in simplest terms.  Wondering the specific instances where it is set. Tried to research on net and found two answers.

1.  XOR of a carry into the sign bit and a carry out of the sign bit.

2. For addition, set when positive num + positive num = positive num and when negative num + negative num = positive num.

For subtraction, set when negative num - positive num = negative num and when positive num - negative num = negative num.

Anyone have a good description?

Tim

[kef · Accepted solution]

In real world, when we add positive number to positive number we expect positive answer. Sudden negative result is oVerflow.

Adding negative to negative shouold give negative result. Positive means oVerflow. 

And subtractiion is similar to addition, except the sign of one of addend.

HC12 CPU manual gives such V bit equation for ADD

V = D15 • M15 • /R15 + /D15 • /M15 • R15

where D15 sign bit of one addend, M15 - sign bit of second addend, R15 - sign bit of result.

So adding V is set when either 1) both arguments are positive and result negrative, or 2) when both args negative and result positive.

for SUB

V = D15 • /M15 • /R15 + /D15 • M15 • R15

[tupdegrove]

Thank-you for the details.

Just for the record, I meant to say:

2. For addition, set when positive num + positive num = negative num...

Tim