Watchdog Timer Timout Reset or Interrupt Config

[David_L]

I've come across what looks like conflicting info in the reference manual regarding the outcome of a watchdog timer timeout. Seems to show up even in the current revision 4 of the docuement.

If you read the text of Section 13.5.4 it states that "...resulting in a watchdog timer interrupt or hardware reset, as programmed by CWCR[CWRI]". This sounds like we have a choice in the outcome based on the set value of this bit.

If you then go to Table 13-6 on the next page which describes the bits in the CWCR register it assigns the following meanings to the CWRI bit.

0 If a timeout occurs, the CWT generates an interrupt to the processor core....

1 Reserved. If a 1 is written, undetermined behavior will result.

So, it seems that what looks like the option to select a hardware reset is invalid or not working? There is a note about using the interrupt to to generate a "soft reset" It almost sounds like this is a workaround for the hardware reset not functioning? Can anybody shed some light on this?

Thanks,
Dave Lundquist

[mjbcswitzerland]

Hi Dave

I believe that only an interrupt is possible - see also the following:
http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=1048&query.id=4024#M1...

However this is not so bad since it can be solved by using the soft reset in the interrupt routine and setting the interrupt to highest priority (only forever loop with disabled interrupts would fail - but this is usually not an issue). Here is the uTasker solution:

// Initialisation
(PNQPAR &= ~(0xc0));     // configure NQ 3 as input
if (!((PORTIN_SETNQ & PORT_NQ_BIT3))) { // If NQ is not pulled down
    CWCR = (CWE | WATCHDOG_2_SEC | CWTA | CWTAVA | CWTIF);
    fnSetIntHandler(SW_WD_VECTOR, (unsigned char *)sw_wdog_timeout);
    IC_ICR_0_8 = (INTERRUPT_LEVEL_7 | INTERRUPT_PRIORITY_7);
    IC_IMRL_0 &= ~(SW_WDG_PIF_INT_L | MASK_ALL_INT);
}
else {
    CWCR = 0;                // watchdog disabled
}

// Watchdog retrigger called every 200ms
CWSR = 0x55;                 // retrigger the software watchdog
CWSR = 0xaa;                 // using this two byte sequence

// Watchdog interrupt
static __interrupt__ void sw_wdog_timeout(void)
{
    RESET_RCR = SOFT_RST;   // command a soft reset of the board
}

Note that when using the BDM with active watchdog, the watchdog will fire when a break is reached (I don't know of a method to freeze the watchdog in debug mode) and therefore the watchdog activation has been made conditional on a port input (NQ bit 3 in this case) so that a strap to ground disables the watchdog for the debugging session.

Regards

Alban fixed link.

Message Edited by Alban on 2007-02-11 07:04 PM

[SimonMarsden_de]

I've noticed the same thing, and it affects the manuals for several different ColdFire processors.

I remember that when the Watchdog Timer was first documented, the CWRI bit was supposed to select the behavio[u]r - i.e. 0 = interrupt, 1 = reset. However, later manuals were changed to make '1' a reserved value.

I suspect that the hardware to give the reset behaviour didn't work for some reason, and the manual got fixed in one place but not the other.