V1 (mcf51jm128) IIC problems

[sps]

I'm trying to setup the mcf52jm I2C controller and having problems I did not see on V2 parts (thought this was a quick 1-hour job!). The example code in AN3464 does not seem to work (although the V2 examples are fine). I find the def's in the V1 headers do not properly set IIC register values. For example, lines like:

IIC1C1 &= ~IIC1C1_MST;  // do not correctly write and will not generate the stop

However, editing to:
IIC1C1 &= ~IIC1C1_MST_MASK;  // correctly generate a stop condition

Once I fix that, it's very buggy (hangs) on repetitive reads or writes (i'm trying to setup an eeprom). Scope SCL/SDA timing looks fine and is nicely adjustable.

Are there any example I2C read, write, and init routines that are known to work on the mcf51jm128? I'm using the PEMicro board for testing. Other controllers on the part have setup w/no problems (I'm paying for that now). This is a different version CW than I use for V2 parts. Is it something in CW I have setup wrong?

Thanks -

[JimDon]

I have not tried the code myself, but is a V1 IIC example in here:
(Demo board\V1\IIC_Master)
http://www.freescale.com/files/microcontrollers/doc/user_guide/QE128QRUGSW.zip

Tell us if it works.

[sps]

Thanks for the tip Jim. I had not even thought to look at the RUGSW files. I did catch an error looking at that I2C example. I also have some interesting observations looking at the example code (some we may not allow in a product):

- they don't use the header defs when programming the registers, just using the hex value. So much for all those cutesy header files we like in CW.
- they call a simple for-loop counter delay through some transactions. My routines work if I do that.
- the transactions are done within the ISR - not knowing how many bytes the caller wants to transfer or how long you may be in the ISR.

Anyway - the code is a good example to check my order and flag testing sequences.

Thanks again,

Message Edited by sps on 2008-11-04 02:22 PM