Hi guys,
Is there an app note on how to use Software Interrupt with the Coldfire V1 core? I'm using QE32 and need to force reset in certain circumstances... With HCS08 that was pretty easy but with Coldfire V1 I'm having problems undestanding how to use it.
An app note or an example will be greately appreciatted.
Kindest Regards,
Carlos
解決済! 解決策の投稿を見る。
Are you running under the debugger? Perhaps you have the debugger set to intercept the exception?
On my 51JM128, when I clear CPUCR, I get the reset. So this seems pretty odd.
You have verified CPUCR is clear?
Hi,
If you just want to force a reset on CF V1 (51QE and 51JM), what I do is:
asm {
move.l #0x00000000,d0
movec d0,CPUCR
trap #0
};
I also have an example of using the sw interrupt in the skeleton.zip archive at the bottom of this page:
http://www.cpustick.com/downloads.htm
You can see in sources/zigflea.c that zb_pre_isr() is invoked by hardware at level 7, which then uses a sw interrupt to invoke zb_isr() at level 4.
Basically, I used to use nested interrupts in my code, but have since stopped doing that (because HCS08 and HCS12 could not).
-- Rich
Instruction moveq.l #0x00,d0 is shorter, than the instruction move.l #0x00000000,d0
Thanks a lot guys...
It seems like it should work if I can get passed the exception handler.
Can you please help me in sneeking this one past the goalie (the exception handler)?
Many thanks,
Carlos
Hi
I'm also trying to force a RESET in software on the MCF51JM128 - I tried the solution above, but I can't get it passed the exception handler. Did you ever get it right?
Does anyone know of a neat way to force a reset and get around the exception handler?
Thanks, Norman
Once you have CPUCR cleared, an illegal instruction or an illegal address should cause a reset... Maybe you can try accessing an illegal address (like 0xbbbbbbbb or 0xdddddddd) and see if you get your reset... Can you confirm CPUCR is clear?
From the RM:
> CPU accesses to those parts of the memory map marked as reserved in
> Figure 4-1 result in an illegal
> address reset if CPUCR[ARD] = 0 or an address error exception if CPUCR[ARD] = 1.
According to the debugger:
CPUCR[ARD] = 0
CPUCR[IRD] = 0
I do note that bit 8 is set, but it is a reserved but and so I don't know what it does.
I tried a few what I think are illegal instructions like asm (jmp 0); asm (jmp 0xbbbbbbbb) and a few illegal moves, but each time the exception handler takes over.
I even tried turning on the low voltage detect at 5V (in a 3.3V system). It simply won't reset. I have resorted to shorting the reset pin to the IO next to is and doing a hardware reset. It obviously works, but is really ugly.
Can you try "*(char *)0xbbbbbbbb = 0;"?
Thanks for the advice, but no, this processor is bulletproof.
My code:
void kill(void)
{
*(char *)0xbbbbbbbb = 0;
}
dis-assembly:
0x0000f904 <kill>: clr.b d0
0x0000f906 <kill+2>: move.b d0,0xBBBBBBBB (0xbbbbbbbb)
off to the exception handler we go.......
asm __declspec(register_abi) void asm_exception_handler(void)
{
link a6,#0
lea -20(sp), sp
movem.l d0-d2/a0-a1, (sp)
lea 24(sp),a0
/* A0 point to exception stack frame on the stack */
jsr mcf_exception_handler
movem.l (sp), d0-d2/a0-a1
lea 20(sp), sp
unlk a6
rte
}
seems to end up at:
VECTORDISPLAY
("Error on operand write\n");
Are you running under the debugger? Perhaps you have the debugger set to intercept the exception?
On my 51JM128, when I clear CPUCR, I get the reset. So this seems pretty odd.
You have verified CPUCR is clear?
Hi Rich
You're a legend!!! Yes, the debugger was intercepting the exception.
so to end this topic, the code below resets the processor (just not with the debugger running).
void
{
*(
kill(void)char *)0xbbbbbbbb = 0;// force a reset
}
Many thanks for your help.
Possibly, a few NetBurner application notes about V2 interrupts will be helpful:
http://www.netburner.com/support/technical_documents.html
then search for word "interrupt".
Note, that NetBurner implementation of uC/OS system library includes the dedicated function ForceReboot(). Try to find the similar function for your OS.