Hi
The M52259 can operate to 80MHz. To achieve this, the 48MHz input can be divided by 6 and then the PLL multiplied by 10.
The UART is clocked at the bus speed, which is half of the CPU speed (40MHz max.) and uses a 16x clock. The minimum divide value is 2, which means that the maximum baud rate that is possible is 1.25MHz.
Note 1: The baud resolution is not good at high speeds (next smallest step down would be 833.333kHz using divide by 3.
Note 2: The UARTs can be clocked alternatively from DTINn pins (at x1 or x16). This would allow fine speed adjustment assuming that the input speed can be controlled accurately. The maximum clock speed that can be applied to DTINn is with a period of 3 x tCYC which I think is about 26MHz with 80MHz PLL (tCYC seems to be the CLKOUT period but is not explicitely defined in the data sheet). There is no maximum baud specified in the data sheet for the UART itself in this mode, which suggests that up to 26MHz may be possible in x1 mode using this technique - can Freescale confirm?
Regards
Mark