/TA and /CS timing for MCF5329

[logiclab]

We are developing a new system based on ColdFIre MCF5329 that will be interfaced with two TI DSP with HPI interface and with a compact flash. We have a problem to understand the FlexBus timing related to /TA and /CS signals.

When /TA is recognized as low, the /CS is negated by processor the next clock rising edge? Or the rising edge of clock after /TA is negated? In other words, the ColdFire CPU wait the rising edge of /TA to negate /CS or always negate /CS the cycle after /TA is sampled low?

There is any difference between auto acknowledge enable and disable when we use /TA to terminate the access for both of them?

Thanks!

[TomE]

> ColdFIre MCF5329 that will be interfaced with two TI DSP

The MCF5329 has an internal EMAC that can execute DSP-like instructions at 240 MMAC/s. What's the comparison between that and what the external DSPs can manage? Is anyone using the MAC/EMAC for anything interesting?

[logiclab]

Yes! I know the DSP capability of MCF5329 but for our application we need more DSP computing performance. We will use a parallel architecture with two TMS320F6747 @ 375MHz with 3000 MMACS.

[TomE]

MCF5329 Data Sheet Section 5.6.1 gives the timing diagrems.

MCF5329 Reference Manual section 17.4.4 gives the state diagrams and descriptive text.

Figure 17.8 looks like it should answer your question.

When in doubt, connect a CRO or logic analyser to your development board and see what you can measure.

TI might have some good Application Notes on interfacing their HPI interface to other processors. Here's somewhere to start (reference on HPI interfac to Freescale MPC860):

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/46895/167921.aspx

[logiclab]

Unfortunately we haven't a deveolping board... we have only schematics of LogicPD

[TomE]

> Unfortunately we haven't a deveolping board... we have only schematics of LogicPD

Buy one. It is the only way to get questions like these answered fast and accurately. What is it worth to you not to waste a week or a month. What is it worth not having to scrap your first board. Or your second. Or your fourteenth (I've seen that :smileyhappy:.

I said:

> > TI might have some good Application Notes on interfacing their HPI interface

> > to other processors. Here's somewhere to start (reference on HPI interfacing to Freescale MPC860):

Have you searched for and read those? TI are the experts here.

The Freescale/Coldfire/PPC bus interfaces are fairly similar, possibly all the way back to the first PPC chip in the first Power Macintosh. The CPU Core was IBMs, the application was Apple's and the bus interface came from the Motorola 88000.

So if you don't like the data sheet or reference manual for your current CPU, then start downloading and reading the data sheets and reference manuals for other ones in the family, or even in previous families. If you can find something old that matches (like a motorola MPC860 manual) you may find it more detailed and better written.

A TI App Note that says how to connect to an MPC860 together with the MPC860 Data Sheets and Reference manuals compared with the ones from your current chip could answer all your questions.

> For internal termination, when external device assert FB_TA, what's happens?

Either nothing because the hardware is set up to ignore the external one in this case, or more likely, the internal "wait state generator" generates an internal TA and it is combined with the external one and "first one wins". But why would you design hardware that provides a TA and then program one to be generated internally as well? You should use one or the other. If the internal one happened and the external device wasn't ready then you've read bad data and don't know it. Also, the external device would still be cycling, now out of sync with the main CPU. That would be dangerous too.

If you're trying to catch an error condition where the external device didn't respond, then you want a bus timer to generate an error trap or error interrupt so you can detect and recover from this condition.

> For external termination, the external device should negate FB_TA, ...

> What's the meaning "should" in the sentence in state S2?

You don't have to. It isn't compulsory. If it doesn't drive FB_TA then the bus will probably lock up forever. Or until any provided and programmed "bus timer" goes off. Or until the CPU Watchdog resets the whole thing. If you want the cycle to complete properly then it probably means "must".

Tom

[logiclab]

Thank you Tom,

but we don't lik to spent hundreds of dollars to have an information that are not present in the data sheet...

You wrote: Have you searched for and read those? TI are the experts here.

Yes! I've found a very interesting AN of Ti that explain how interface MC68360 to TMS320C6000. This application use a logic for /TA that are similar to the logic used on my board.

 The logic works properly only if /CS is negated by ColdFire after /TA is sampled low. I need this information...

You wrote: If you're trying to catch an error condition where the external device didn't respond, then you want a bus timer to generate an error trap or error interrupt so you can detect and recover from this condition.

Yes! I know... but the problem is that for a bug. In device errata document, section SECF017, you can read:

This device does not include a bus monitor or watchdog timer capable of forcing the termination of a hung FlexBus access. [...] There is no on-chip fail-safe to exit from the hung bus state. The system needs to assert TA to terminate the hung cycle or reset the entire device.

So, it's very dangerous working with external termination only! We will set all CS with internal termination and, for CS used to interface with devices that use /TA, the wait states will be configured with value greater than maximum delay time reported in the device data sheet.

I understood that "should" means "I don't have to", but the question is... If /TA is not negated, /CS will negated by ColdFire the next cycle or CPU waits the rising edge of /TA?

If /TA low, lock up the bus forever, I think that in the reference manual there would be wrote "the external device should negate FB_TA to prevent hung FlexBus". In state-transition diagram in section 17.4.4 there isn't a stay condition in S3 where CPU wait the external device negate /TA. So, I think that if /TA remains low the access ends with S4 in any case.

Thank you Tom for your answers!!!

Bye, Daniele

[TomE]

> but we don't lik to spent hundreds of dollars to have an information that are not present in the data sheet...

You can never have too much information. Development boards are cheap insurance.

> This device does not include a bus monitor or watchdog timer capable of forcing the termination of a hung FlexBus access.

So if it is important for you to catch this sort of problem you need to add EXTERNAL HARDWARE to catch this case.

If you have any programmed logic on your boards you could put this function into a corner of them, otherwise it could be as simple as a 74VHC132 quad schmitt NAND gate.

Rig two gates up as an RS flip-flop, then put an RC-diode delay from the chip-select into "set" and a GPIO pulled low with a resistor into "clear". Remove the "clear" signal as part of your startup (program the pin as an output and drive high). Connect the output through a diode to TA and also to another GPIO status pin, preferably one which can generate an interrupt.

If the chip select is down long enough for the RC to charge up,the flop-flop sets, terminates the bus cycle and generates an error interrupt.

Of course you might be able to program the wait state generator to terminate the cycle, but you won't know that it has happened.

Here's a (bad) idea. Assuming data transfers are in "bursts" that you know the start and end of, program a timer with a "long timeout" (milliseconds) at the start of a "burst" and stop it at the end. Have the timer output pin connect through a diode back to TA (to terminate any stuck cycles) and also to generate an interrupt that will tell you that it timed out. There's quite a lot of software overhead in this managing the timer, but it might be easier to hack in than to add another chip and two GPIOs.

[logiclab]

In section 17.4.4 table 17-7 you can read in state S2 - All "For internal termination, FB_CSn is negated and the internal system bus transfer is completed. For external termination, the external device should negate FB_TA, and the FB_CSn chip select
negates after the rising edge of FB_CLK at the end of S2."

State S2 is reached when "FB_TA is recognized asserted, then the cycle moves on to S2" as wrote in state S1.

For internal termination, when external device assert FB_TA, what's happens?

What's the meaning "should" in the sentence in state S2? If external device doesn't negate FB_TA, the coldfire always negate FP_CS the next cycle? This is the critical point for our application! In the manual and data sheet I've not found a clear and unequivocal explanation.