Spurious Interrupt on coldfire 5329

[Koen]

Hi,

I'am working on a coldfire CF5329. When I want to use the external interrupt IRQ1 a spurious interrupt occur.

When I start the coldfire it works fine... no external interrupts. When I start my external device, it generates a interrupt (10µs low) every 500µs. Immediatelly after i switch my external device on, a spurious interrupt will occur.

I there a reason for this interrupt??

My IRQ1 level = 5 and my SR register is set to 0x3000

Thanks,

Koen

[mccPaul]

A spurious interrupt is generated because the CPU cannot determine the interrupt source. (see section 14.3.1.3 in the reference manual).

You need to check if you have correctly set the Interrupt Mask Register (mcf5329 reference manual section 14.2.2 - in particular read the NOTE) and if you have correctly set the Interrupt Control Register for your interrupt (Section 14.2.9).

Paul.

[Koen]

Hi,

I think my registers are set correctly for IRQ1 (source 1 intc0)

Global level -> SR = 0x3000

INTC0_ICR1 = 5;               

INTC0_IMRL = A3FFFF01;

GPIO_PAR_IRQ = 0;

With these settings a spurious interrupt will occur. Mostely i received the IRQ 4 a 5 times correctly but then, it fails...

Koen

[mccPaul]

Hi Koen

Can you confirm that you INTC0_IMRL is set to the value you want? I can understand why you have the I2C and UARTs unmasked, but you have unmasked all of the edge port interrupts. Did you mean

INTC0_IMRL = 0xa3fffffd ?

A spurious interrupt exception occurs because the IMR has been changed between the time when an interrupt source has been recognised, and the time the core comes to determine the highest priority source at that level.

The IMR is used twice - during interrupt recognition, the interrupt controller uses it to determine if there are any active requests. Then there is a short delay while the interrupt controller works out it the interrupt's level is greater than that of the SR. If it is, the interrupt's level is passed to the core. The core then uses the IMR to find the highest, unmasked source at that level. If the relevant bit in the IMR is changed from 0 to 1 before the final step, you get a spurious interrupt.

Are you using INTC0_IMRL to mask and unmask your interrupts a lot? If you use INTC0_IMRL in an ISR to mask and unmask your source you may get this problem.

Paul.

[Koen]

Hi,

The value of INTC0_IMRL is the value I want. All IRQs are connected with an FPGA. At this moment I only use IRQ 1 and IRQ 3, but I masked them all.

During a ISR I never change the INTC0_IMRL state. The INTC0_IMRL is set at start-up, and after this set, the value is never changed.

Sometimes the IRQ works fine for a certain time, but at an unexpected moment (afters some ms) it generates an spurious interrupt.

Koen

[mccPaul]

Hi

Are you using level or edge triggering for the edge port?

Could there be some minor timing problem where you may have an interrupt signalled to the interrupt controller, but you are already dealing with a previous interrupt so the interrupt is cleared before the interrupt controller has identified it? In other words, you have two interrupts, but the ISR only executes one time and clears both interrupts.

I am guessing, but without seeing your code it is hard to do anything else.

Cheers,

Paul.