Question on MCF5275RM.pdf timing figure pg 291

[kerkchoonhuei]

In attached figure, I have a few concerns which need confirmation.

1) Figure 15-2, #OE is indicated as low during write cycle. #OE should be pulled high instead?

2) Figure 15-2, #CSn and #BSn is always pull low during the write cycle. They should be toggling as per yellow waveform?

3) Figure 15-3, D[31:0] is doing Write operation. It should be Read operation?

[miduo]

Hi,

Sorry it is really the manual error as Tom mentioned. I am supposing that this is caused by "paste" from other figure.... So had reported but not sure if can been corrected because it is so old part and do not have much resource on this regard. Sorry.

B.R.

Fang

[melissa_hunter]

Hi,

Items 1 and 3 are errors. However item 2 is correct as shown. The bus cycle is a burst, so /CS and /BS stay asserted throughout the entire burst (they don't toggle). If as Tom suggests you refer to the burst diagrams in the EIM chapter, you'll see that /CS and /BS don't toggle during bursts.

Regards,

Melissa

[TomE]

Yes, it looks like you've found a bug.

I think that diagram is only present to illustrate the "Secondary Wait States" and whoever drew it didn't bother with the rest of the signal.

I suggest you read the Data Sheet for proper bus timing information (but the one for this chip isn't that good) and also refer to this chapter which seems to be the one that details the signal timing properly:

Chapter 16> External Interface Module (EIM)

Tom