The CPU comes out of reset by fetching the reset vector from address 0x00000000.
> my program is stored where it should be (internal flash 0xF0000000).
The MCF5282 lite evaluation board has 16M of RAM and 2M of FLASH. Those chips only have 512k of internal FLASH so it must be set up in "Master Mode" to use the external.
Read:
6.3.2 Flash Base Address Register (FLASHBAR
Chapter 27 Chip Configuration Module (CCM)
> However, when performing a reset, the debug program native to the is launched.
That development board is doing something interesting and tricky. The chip can be either in Single Chip mode (internal RAM and FLASH only) or Mater Mode (with external FLASH). That board is obviously running in Master Mode.
The EVB Manual doesn't mention running the board in Single Chip Mode. It does list in a table how to make it do this, in "Table 1-7. SW1-[7:5] Chip Configuration Mode".
It also mentions "1.3.6 User’s Program" which documents how to run the user program in the upper half of the external FLASH from reset.
Is your final product to be a Master Mode or Single Chip Mode setup?
Tom