Turrican,
The following is an answer to your question and some extra info for those that may be reading this post.
The MCF547x and MCF548x products use a true DQS block that adjusts on a per-byte-lane basis. This means that the most critical delays are within the byte lane.
The general rule-of-thumb that I use is roughly 180ps/inch for trace delay on a FR4 based PCB board. It can vary depending on dielectric material and trace topology. The propagation of signals within the packages for this family of parts is very close to that of a FR4 PCB board. So it would take an inch of trace difference within the package to equate to ~180ps of delay between the longest and shortest path within the byte lane.
That said...Freescale does try to match delays within our packages, and specifically within byte lanes. If all propagation delays are matched within the package, then you just need to match them on the board and things will go pretty good because all the signals within the byte lane will arrive at the same time.
In practice, you need to match each data byte lane with its associated DQS and DM.
If you are tempted to route all the DQS signals together and then route the data bus seperately, then you will probably run into issues.
Hope this helps.
-JWW
