I used the MCF54418 chip and enabled the internal watchdog timer to reset the system when it times out. However, after stopping the timer refresh, I expected a system reset but instead, the core halted. Can you clarify?
Note: Only PIT0 interrupt is enaled and software runs on Internal SRAM.
I have activated the CWRI on the CWCR with 10 If a time-out occurs, the CWT generates a system reset and RSR[WDRCORE] in the reset controller is set.
CWE is 1
CWT is prperly configured for 268ms.
The same configuration works when the code runs in external flash. However, when I move the code into Internal SRAM from external flash, then system reset does not happen. The system is halted.
> CWCR with 10
You need CWRWH set if you want the watchdog to run while halted. If the CPU is halted, it won't run.
I suspect there's something going wrong with your code running from internal SRAM. Something that makes it halt. You should turn CWRWH on (you didn't say it was on, so I assume it isn't) and see if the reset now works. Then find out why the CPU is halting. Do you have a debugger connected? The stack should have stack frames recording why this happened. It either executed a HALT instruction somehow (the PC should point to something interesting) or it got a double bus fault.
If you posted your code or the line or lines that write to CWCR so we can check all the bits, it would make it easier to give suggestions.