MCF5407 SRAM Read/Write bus cycle

[FNapo]

Hello,

I wanted to have more information regarding read & write bus cycle for SRAM memory. Could it be possible to have the time for normal read and normal write on external bus interface (min and max).

I studied the 20.3 Input/Output AC Timing Specifications part of the datasheet and i found around 29 ns, but I'm not really sure about the method.

Thank you for your help.

Best Regards.

[TomE]

The MCF5407 Chip Select Controller is relatively simple. The only option you have is the number of Wait States to add to the cycle. This is detailed in the User Manual in Section 10.4:

https://www.nxp.com/docs/en/data-sheet/MCF5407UM.pdf

Chapter 18 gives the Bus Timing Diagrams. You should use this as your reference.

Chapter 20 gives the timing details, as you've found. You have to add and subtract all of the individual parts of the bus cycle in order to get the specific measurement that you want.

"Time for normal read and write" depends on a lot of different signals. There's the time from the Address, from Chip Select and from Read/Write. Then there's the setup time to the read. The clock isn't constant (you can run the CPU at different clock rates) and you can have different numbers of wait-states, or you can have externally-generated wait timing.

If you have Address and Data Buffers you have to add all of the delays in those chips. If you're generating READ and WRITE data lines from the Chip Select and Read/Write lines, you have to add all of the delays in that logic. All of that should give you a maximum access time, which you compare to the worse-case read time for the SRAM. Which in most cases won't work (the read time will be 30ns and the chip will be 110ns or something like that). So you then add enough Wait States in the Chip Select Programming to meet those timing requirements.

Conveniently, the CSCRn registers default to 15 wait states, so it is guaranteed to work from Reset, just a lot slower than it can. Part of the startup sets it to a properly worked out value (for CS0, the Boot one), and then you set it to the right values for everything else.

This is really simple, and has been like this for at least 30 years with these sort of chips. You're lucky as "modern" CPUs can have as many as 256 BYTES of configuration data in their memory controllers (for DDR2 and so on) that you have to get right or they won't work properly.

The Address and R/W lines transition (B10) Max 8ns after the rising clock.

The Chip Select then transitions (B13) Max 0.5(C1)+8ns after the same rising clock, where "C1" is the cycle time. In other words, Max 8ns after the Falling clock edge after the reference rising one.

The Data has to be present (B1) 7.5ns before the rising clock, and held for (B2) 1ns after.

That second clock the Read happens on is shows better in Diagram 18-6. There are 6 half-clocks in a read cycle named S1, S2, S3, S4, S5, S6. The Address/RW lines change at the start of S1, CS in S1 and the data is read at the start of S4. So 4 half-clocks from Address and three half-clocks from Chip Select. MINUS the B10 and B13 delays, MINUS the Setup Time. Then ADD the number of Wait States, which result in cycle S3 being extended by two half-clocks per wait state.

So B13 + 3C1/2 + B1 + WS*C1 + (CS to RD delays) + (Data Buffer Delays) > (SRAM Read Time)

Or something like that.

Tom

[TomE]

I had some more ideas and so I "Edited" my post. Then the "Verification Failed" and the "Edit" went away. So I'm going to post the whole thing AGAIN with the edits because the Forum System doesn't let me do this easily.

===

There is no one simple answer to that question. This isn't a 1980's PIC chip or a Z80 or something equally simple. The bus clock is programmable and variable. The number of bus-clock-length wait-states is programmable. In larger systems there's usually logic or PLDs decoding the bus signals, which adds circuit delays. Bus data buffers add delays. You have to add all of these up yourself.

The MCF5407 Chip Select Controller is relatively simple. The only option you have is the number of Wait States to add to the cycle. This is detailed in the User Manual in Section 10.4:

https://www.nxp.com/docs/en/data-sheet/MCF5407UM.pdf

Chapter 18 gives the Bus Timing Diagrams. You should use this as your reference to understand the cycle timing.

Chapter 20 gives the timing details, as you've found. You have to add and subtract all of the individual parts of the bus cycle in order to get the specific measurement that you want.

"Time for normal read and write" depends on a lot of different signals. There's the time from the Address, from Chip Select and from Read/Write. Then there's the setup time to the data read.The bus cycle has 6 stages plus optional wait states. The length depends on the programmed clock rate.

If you have Address and Data Buffers you have to add all of the delays in those chips. If you're generating READ and WRITE data lines from the Chip Select and Read/Write lines, you have to add all of the delays in that logic. All of that should give you a maximum access time, which you compare to the worse-case read time for the SRAM. Which in most cases won't work (the read time will be 30ns and the chip will be 110ns or something like that). So you then add enough Wait States in the Chip Select Programming to meet those timing requirements.

Conveniently, the CSCRn registers default to 15 wait states, so it is guaranteed to work from Reset, just a lot slower than it can. Part of your startup code should set that to a faster value, and then program all the other chip selects to values matching the hardware design.

This is really simple, and has been like this for at least 30 years with these sort of chips. You're lucky as "modern" CPUs can have as many as 256 BYTES of configuration data in their memory controllers (for DDR2 and so on) that you have to get right or they won't work properly.

The Address and R/W lines transition (B10) Max 8ns after the rising clock.

The Chip Select then transitions (B13) Max 0.5(C1)+8ns after the same rising clock, where "C1" is the cycle time. In other words, Max 8ns after the Falling clock edge after the reference rising one.

The Data has to be present (B1) 7.5ns before the rising clock, and held for (B2) 1ns after.

That second clock the Read happens on is shows better in Diagram 18-6. There are 6 half-clocks in a read cycle named S1, S2, S3, S4, S5, S6. The Address/RW lines change at the start of S1, CS in S2 and the data is read at the start of S4. So 4 half-clocks from Address and three half-clocks from Chip Select. MINUS the B10 and B13 delays, MINUS the B1 Setup Time. Then ADD the number of Wait States, which result in cycle S3 being extended by two half-clocks per wait state. So adjust Wait Status until:

B13 + 3C1/2 + B1 + WS*C1 + (external CS to RD delays) + (Data Buffer Delays) > (SRAM Read Time)

Or something like that. Then build it and check it all with an oscilloscope.

Tom

[FNapo]

Thank you very much for your help

[Hui_Ma]

Hello,

MCF5407 is a quite old product, there lack of relavant document resource.

I would recommend to refer MCF5282 user manual chapter 13 about ColdFire external bus info.

Wish it helps.

Mike