MCF5301X Drive strength settings

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MCF5301X Drive strength settings

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1,389 Views
Dec
Contributor III

Hi,

 

We've just been reviewing the processor configuration on our board using the 53014.

According to the datasheet the drive strength of various flexbus signals can be set.

The strength is set by 3 bits as follows :

000 Half strength 1.8V mobile DDR

001 Full strength 1.8V mobile DDR

011 2.5V DDR1

111 3.3V SDR

All other values are reserved.

 

On reset the default settings for these signals is 110 which falls in the reserved area.

 

Does anyone know what the actual drive would be when set to 110 as I can't find any reference to that setting other than saying it's reserved.

 

Thanks

 


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miduo
NXP Employee
NXP Employee

Hi, Paul

Sorry we do not have the IBIS module for the MCF5301X parts. As for the reserved 110, please try not to use this state as the manual mentioned it is a reserved. Please make sure to reprogram the MSCR with the desired, valid value as part of the DDR init sequence.

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TomE
Specialist I

BINGO!

I knew that all this needed was a bit of archaeology.

I searched Freescale's site for "1.8V DDR2 Full strength" and got a match on:

http://cache.freescale.com/files/32bit/doc/data_sheet/MPC5675K.pdf

That Data Sheet contains the table:

Table 44. Mode configuration for DRAM pads

  Configuration[1] Mode

  -------------------------------------------

  000              1.8 V LPDDR Half Strength

  001              1.8 V LPDDR Full Strength

  010              1.8 V DDR2 Half Strength

  011              2.5 V DDR

  100              Not supported

  101              Not supported

  110              1.8 V DDR2 Full Strength

  111              SDR

  [1]Configuration is selected in the corresponding PCR registers of the SIUL.

Those values are an exact match for the table for the MCF53014, together with the "mystery reserved values" you've been able to find out about.

So the silicon in the MCF53014 looks like it was cut-and-pasted across from the MPC56xx series of chips, and the section of the manual you're reading was an edited cut-and-paste too.

The interesting question is "what do the MPC pads default to"? That's harder to answer than it looks as there are hundreds of "pad control registers" in this chip.

The Data Sheet lists the different characteristics of all the supported "Drive Modes", but there's nothing in the Reference Manual matching any of the keewords that are in the Data Sheet. The only things in the PCR registers of the SIUL are 8 selectable SRC (Slew Rate Control) bits, but there's no other documentation of these. They might be the ones controlling the pins, but I couldn't program a product from this information.

I suggest you look through the data in the MPC5675 Data Sheet, specifically the "3.19.x DRAM pads electrical specification" sections.

Tom

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TomE
Specialist I

Maybe the MCF5301x Data Sheet gives some details. It has AC Timing sections, so it should list the different timing and signal strength for each mode.

Section "5.4 DC Electrical Specifications" lists that SDVdd can be 1.8 (Mobile DDR), 2.5 (DDR) or 3.3 (SDR). It lists the output voltages at "5.0 mA for all modes", but that doesn't seem to include the "half strength" modes.

Sections "5.7.1 SDR SDRAM AC Timing Characteristics" and "5.7.2 DDR SDRAM AC Timing Characteristics" don't give any specifications for half/full either.

I'm surprised that the Data Sheet is Revision 5, dated March 2010, following on from Revision 3 dated Aug 2009, but 5 years after that is still marked "Preliminary—Subject to Change Without Notice". I wouldn't use a chip until warnings like that in the supporting documentation went away.

From reading the Data Sheet I wouldn't use this chip with SDR. There's no "Half Strength" mode listed. We have a design with an MCF5329. It defaulted to "Maximum Strength", but was unreliable as it was overdriving the SDRAM chip which were then failing. We had to drive our 3.3V SDRAM with the "1.8V Mobile DDR Half Strength" setting for it to be reliable. That's a bit of a brain-bender having to set it up like that.

Which underscores the fact (independently confirmed by Freescale and reading the IBIS file) that these labels for these "modes" are indications of what these settings might be USEFUL for rather than what the settings actually ARE. These "Marketing Descriptions" seem to have been copied to data sheets for lots of products. They are better described (for the MCF5239) as 10/20/30/50 pF drivers settings. That's probably what they really are in the MPC5675 and MCF5301x as well.

I'm surprised that there seems to be no IBIS file available. There is for the MCF5329 and the latest version of the Data Sheet for that chip (Rev 3) is dated 2008 whereas the earliest MCF5301x one is dated 2009. It isn't as if they're different "generations" of chip and design methodology. Maybe there is an IBIS file but it just didn't get released to the Web Site.

Tom

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Dec
Contributor III

Hi Tom,

Great investigative work, thanks for your help on this.

I don't think I've come across anything quite as confusing as Freescale datasheets before.

When we first used the MCF5301X we used a different package and then discovered not all peripherals worked so we had to switch to BGA. After a lot of prodding Freescale acknowledged the fault but took months to issue an errata during which time I know other companies also had to scrap boards and start again :smileysad:

Quite why they use "marketing descriptions" just confuses the issue further.

Combining your work with feedback from our distributer and Freescale support we have the following :


  Configuration    Manual Description                      Support/distributer feedback

  Mode

  ---------------------------------------------------------------------------------------

  000              1.8 V LPDDR Half Strength                    10pF

  001              1.8 V LPDDR Full Strength                    20pF

  010              1.8 V DDR2 Half Strength                     Capability unknown

  011              2.5 V DDR                                    30pF

  100              Not supported

  101              Not supported

  110              1.8 V DDR2 Full Strength                     Capability unknown

  111              SDR                                          50pF


Our board is probably unusual in that although there is an option to fit SDRAM we've never actually fitted it. I started looking into these register settings after discovering excessive signal overshoot/undershoot on FB_CLK in particular. Although we've not had any issues with the several thousand boards in the field this is something I'd like to improve. All other signals are OK as we fitted series resistors but it looks like we forgot FB_CLK :smileysad:  Changing the drive strength greatly improves the signal but I didn't want to change it without knowing exactly what it was being changed from/to.

Paul

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Dec
Contributor III

I've received another reply from support.

The latest is setting 110 is 1.8V DDR2 Full strength.

They've not indicated what the load driving capability is so I've asked for further clarification.

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TomE
Specialist I

> The latest is setting 110 is 1.8V DDR2 Full strength.

The identical text description for the MCF5329 turned out to be the 30pF setting.

You should simply ask for the IBIS file. Why get the facts filtered through a human?

Tom

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Dec
Contributor III

Hi Tom,

We're trying every approach open to us.

So far we've five settings

000 Half strength 1.8V mobile DDR the pads are capable of driving a 10pF load.

001 Full strength 1.8V mobile DDR the pads are capable of driving a 20pF load.

011 2.5V DDR1 the pads are capable of driving a 30pF load.

111 3.3V SDR the pads are capable of driving a 50pF load.

and finally "110 is 1.8V DDR2 Full strength" which is definitely different to the above four.

This info is really for interest at the moment, might be useful in the future though.

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miduo
NXP Employee
NXP Employee

Hi, Paul

Sorry we do not have the IBIS module for the MCF5301X parts. As for the reserved 110, please try not to use this state as the manual mentioned it is a reserved. Please make sure to reprogram the MSCR with the desired, valid value as part of the DDR init sequence.

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miduo
NXP Employee
NXP Employee

Hi, Paul

Just for a quick update. We are investing this issue now and contacted the designer of this chip to get more information regarding this issue. You will received the more update soon, I am pretty sure. Thanks for your patience.

Fang

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Dec
Contributor III

A quick update on this.

The issue is not yet fully resolved but I've had an update from Freescale.

With the MSCR fields (MSCR_x) setting:

000 Half strength 1.8V mobile DDR the pads are capable of driving a 10pF load.

001 Full strength 1.8V mobile DDR the pads are capable of driving a 20pF load.

011 2.5V DDR1 the pads are capable of driving a 30pF load.

111 3.3V SDR the pads are capable of driving a 50pF load.

They agree that on power up/reset the chip defaults to 110 which is a reserved state but they don't know why that was done.

They also don't recommend the use of that reserved state!

I've asked them to provide details of the drive strength for the reserved states and will post that information when I get it.

All very confusing.


Paul

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TomE
Specialist I

We had a similar problem in 2010 with the MCF5329, detailed here:

https://community.freescale.com/message/67432#67432

Its MSCR_FLEXBUS and MSCR_SDRAM pins are documented as:

  • 00 Half strength 1.8V Mobile DDR.
  • 01 Open drain.
  • 10 Full strength 1.8V Mobile DDR.
  • 11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

That doesn't tell me what the actual drive strengths are.

We got a rapid answer from our distributor, which was that the only up to date documentation for what this means is in the IBIS file.

They're actually 10/20/30/50 pF drive strength, the same as the other pins, but someone was being "helpful" with the above descriptions.

Checking the Reference Manual for your chip, the section you're referring to is:

14.3.6 Mode Select Control Registers (MSCRn)

It is very common for these tables to be wrong. Often they're cut-and-paste copies from other manuals, and things get missed or don't get changed when they should.

The Manual SAYS the default value is "110", and as you say that's "reserved", but what does the CHIP actually default to?

You'll probably find from the IBIS file (as we did) that the four settings are the same as or very similar to the 10/20/30/50pF drive capabilities documented for the other pins for these registers:

14.3.8 Drive Strength Control Registers (DSCR_x)

Tom

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Dec
Contributor III

Hi Tom,

Thanks for your reply.

The chip actually defaults to 110, so it does match the manual but that also means it's reserved :smileysad:

I did try opening a service request but after filling in all the info and pressing submit I just get "An error occurred while processing your request. Reference #97.20c18d3f.1398674632.1d4410d"

Edit : After failing several times the support request has now been submitted.

I'll try going through our distributer.


Thanks

Paul

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TomE
Specialist I

Weire. The IBIS file for the MCF5329 is freely available on that CPU's product page:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF532X&nodeId=018rH3YTLCC2AB2076&fps...

But there's no sign of one for the MCF5301x on its page.

If you go into the Freescale Search page, and search for"Software and Tools", "Simulations and Models", "IBIS" there are 21 matches for various chips, but not for yours.

I'd seriously suggest downloading all 21 Reference Manuals for all the other chips that they do provide IBIS models for and seeing if any of them have the same (or similar) MSCRn registers. If you find one, then read its IBIS files. Also read the Reference Manuals, as the details might be more sensible in one of the other ones.

Searching Freescale for "Mode Select Control Registers (MSCRn)" only gets a hit on your chip, as does a search for "MSCRn", so don't bother with the other chips.

I hope you can get an IBIS document for it. You should get better support through the distributor than through the Service Request. Our distributor has been great on every occasion we needed something like this clarified. I've tried Service Requests, and can't remember any of them getting a result..

Please post back here if you get this sorted.

And the other option which I've also done is to CHANGE those settings to all 8 values while forcing a bunch of pins up and down and monitoring them with a good oscilloscope. Compare with the sensible ones that are properly documented and have 10/20/30/50pF settings. Then see which-one-of-eight matches the documented-one-of-four on the other pins.

Tom

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Dec
Contributor III

Hi Tom,

Thanks for the suggestions. I'll certainly try all combinations and compare with other signals.

It seems the distributor we've used for years, and got on very well with, has lost the Freescale franchise so I'm now in the process of making contact with the new distributor.

I'll report back any findings.

Paul

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Dec
Contributor III

I've had no response to the service request I took out on the 28th April :smileysad:

Our distributer also took out a service request and did get an answer -

Actually this is really a manual typo and sorry for the
confusion this had caused. There has only two bit which control the mode
select. The bit 5 of MSCR1-3 is reserved. So the manual should read as below:

00 Half strength 1.8V mobile DDR

01 Full strength 1.8V mobile DDR

10 2.5V DDR1

11 3.3V SDR

The only problem with this is the 2.5V DDR1 setting produces no signal output when selected.

I've just done a quick test assuming the register is actually 3 bits and tried all 8 possible combinations.

2 produce no signal, but bit 5 of MSCR1-3 definitely has an effect.

I'll ask our distributer to investigate further.

Paul


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TomE
Specialist I

> I've had no response to the service request

The "Help Desk" is there to keep the Engineers from being disturbed.

> The only problem with this is the 2.5V DDR1 setting produces no signal output when selected.

it is remotely possible that is the "Open Collector" setting. The controller in the MCF5329 has four settings and one of them requires pullups on the bus. You could add a pullup resistor to see if that's what is happening with this one.

> bit 5 of MSCR1-3 definitely has an effect.

> I'll ask our distributer to investigate further.

Keep pushing. Eventually someone will look at the chip schematics and find what's really happening.

Tom

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